DE2341222A1 - ARRANGEMENT FOR THE TRANSFER OF INFORMATION FROM A CENTRAL UNIT TO PERIPHERAL UNITS, IN PARTICULAR FOR THE REMOTE INDICATION - Google Patents

Description

STANDARD ELECTRICS LORENZ
SHARED COMPANY

Stuttgart

K. Nigge - 6

Arrangement for the transmission of information from a Central unit for peripheral units, in particular for telecommunications technology,

The task arises that information is transmitted from a central unit to peripheral units have to. The information is then stored in a peripheral unit and triggers certain processes there and issues a response to the central unit, which then provides further information, if necessary to a other peripheral unit transmits.

As a result of the transfer, you keep coming back Breaks on. For example, when searching for a route in telephone switching systems successively the intermediate lines, switching matrices, coupling groups according to free, possible and later searched for paths to be coupled. For this purpose, the marker as the central unit receives the addresses of the lines, etc. to the switching network. The one selected by the address Line, etc., then sends back a corresponding information. If the line is not free, in search for a free line at the same level. If a free line is found, it begins the search in the next stage,

28.5.1973
Ti / Mr

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The received addresses are stored in the coupling network.

Now there is the disadvantage that from the time an address is sent to the time at which the address is in the Coupling network for storage can and must always be a certain amount due to transient processes Time goes by for calming down. In order to achieve an acceleration, it is possible to use very fast uni with low resistance Use transmitter and receiver for the individual wires. In this case, however, a high level of heat loss occurs.

The invention is based on the object of an arrangement for Transmission of information from a central unit to peripheral units with information memories, in particular for the route search in centrally controlled coupling networks of telecommunications technology, with which an acceleration is achieved without having to use low-resistance transmitters and receivers everywhere. According to the invention, this is thereby achieved achieved that an information transmitter in the central unit is provided, from which the respective pending information to all information memories of the peripheral units is transmitted that the information transmitter is switched on with a first clock, that with a second clock whose phase is shifted from the first cycle by such a time that the transient processes for the transmitted Information has ended, the result of the evaluation of the information initiated by the preceding information Process is received and, depending on it, a write command to all or a group of information stores is transmitted, which is only in the information stores becomes effective, which are marked by a signal emitted by a control switch that the control switch

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controlled by a third cycle, the pulses of which are output between those of the second and first cycle, and that the switching takes place directly in some positions by the third clock and in the other positions only with the simultaneous occurrence of the third clock and a certain return signal from the "peripheral units,

This has the advantage that the transmission the information has already been made if it is still being evaluated as a function of the previous information and that immediately after receiving the result of the evaluation, the information "calmed down" up to that point is written will.

A further development of the invention consists in that a write-in core is provided which is sent in parallel to all information memories is turned on and that the control switch marks one memory at a time.

This has the advantage that only the effort can be kept very low. It will be accepted taken that a delay of the transmission takes place with certain further switching of the control switch.

Another development of the invention is that two write-in cores are provided, each of which a depending on the position of the control switch and the return signal transmits the write command that the Write-in cores are alternately connected to the information memory and that the control switch has two each controls successive information stores.

There is the advantage here that also with the forwarding there is no delay in the control chatter,

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for this, however, a second write-in core, which is a particularly fast and therefore complex line, must be used will,

When using the arrangement, it must be considered whether time or effort can be neglected.

The invention will now be explained with reference to the exemplary embodiments shown in the accompanying drawings. Show it:

1 shows a block diagram of an arrangement with a write-in core and

2 shows a block diagram of an arrangement with two write-in cores,

Controlled by a marker M as the central unit, a free path is to be sought in a coupling network KN. Zu.diesem purpose must be looking for a clear path in each of the stages. The respective addresses of the lines, KoppelvM-fold or groups are written into address memories, of which only one is shown per stage in the exemplary embodiment.

In the idle state, the control switch SS is on step s0. If a start command St is given at the beginning of the route search, the condition for the AND circuit U7 is met and the AND circuit U6 is now prepared via the OR circuit 05. With the next clock pulse Tst, the control switch SS is switched to the position si. The control flip-flop FF, which ^{prepares the AND circuit U 1} », is toggled via the output si. From a not

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Established clock pulse generator, three clock pulse sequences are emitted, which occur in the order Tst, Tl ₁ T2, Tst ,,,.

With the now following clock pulse T1, the address chain AK is switched on and sends over the lines WA the first address to the address memory ASpI ,,, 3,

A clock pulse T2 then follows, which is transmitted via the AND circuit U5 and the OR circuit 01 the transmission of a look-in command controls over the line ES. The AND circuit U5 was prepared via the output si and the OR circuit 06.

The time interval between the clock pulses T1 and T2 is selected so that the address transmitted over the line WA is so far is reassured that it can be evaluated, As from the output al of the control switch via the OR circuit 02 and the Level address line SAl only the AND circuit Ul was prepared, is with the incoming over the line ES Write command, the address pending via the WA lines is only stored in the address memory ASpI,

KN _x ,

In the coupling network it is now checked whether the address addressed by the Line switching matrix or switching group is free.

In the meantime, the pulse generator emits a pulse Tst again and the control switch SS switches to the position s2, since the AND circuit U6 was prepared via the output si. Level 1 remains marked via the OR circuit 02. With the then following clock pulse T1, the address chain AK is advanced by one place and it becomes the next Address sent out over the lines WA to the address memory. A clock pulse T2 then follows again, but this cannot take effect via the AND circuit U5, since this

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is not prepared by output s2. With the clock pulse T2 rather, the query and evaluation circuit AA is switched on. The test result in the coupling network was transmitted to the marker via the line AN and as a function of this, either the AND circuit Uli or the AND circuit U12 is enabled, if via the previously transmitted address is no route possible, the AND circuit U12 outputs an output signal via the line NM, which is transmitted via the OR circuit 01 and the line ES as a write command to the switching network and it the address at hand is now written into the ASpI address memory again. As long as there is a free line is found, one address after the other is written into the address memory ASpI in the manner described above.

It is now assumed that a free line has been found. With the clock pulse T2, the AND circuit becomes dinn Uli conductive and via the line M is then via the AND circuit U8, which is controlled by the control switch in the Position s2 was prepared, the AND circuit U6 prepared and with the next clock pulse Tst switches the Control switch SS in position si, the control switch It therefore remains in position s2 until a free line has been found. The same processes take place here as already described for the positions si and s2. The respective attached address is now written into the address memory ASp2. While switching to the position s3, the Address chain AK Preparatory created address not written. If a free path has also been found in the second stage, the control switch switches one after the other in the positions s5 and s6 and it is now searched in the third coupling stage. As soon as the

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The search is successful, the control switch switches over the Position s7 in position s0, in position s7 the control flip-flop FF is tilted back via line R. and an end signal is sent out via the line E. The addresses of the selected ones are in the address memories free sections of the way are saved and it can now be paired.

The address chain for the exemplary embodiments is assumed to be a circulating binary counting chain which can count as far as e.g. kick off. Since, as a rule, several addresses have to be checked for each level during normal operation, the switching time from one level to the next is not so much a delay. In order to shorten the search time even more, the arrangement shown in FIG. 2 can be used. Identical elements are provided with the same reference symbols and similar elements are identified by an additional ' .

The processes when switching on proceed as already described for Fig.l. When the test result is queried for the first time with the clock pulse T2, the control switch SS ^{1 is} in the position s2 ^f . In this position, the AND circuits U1 and U2 are prepared via the OR circuits 02 and 03. At the same time, the AND circuits U13 and Ul ^ are prepared via the OR circuit.

If no clear path has been found, the line is over NM fulfills the condition for the AND circuit U12 and a write command is transmitted over the line ES1.

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Since this line is only connected to the AND circuits Ul and U3 is, the preparatory created address is despite the marking of two levels over the lines SAl and SA2 are only written into the address memory ASpI.

If, however, a free line was found, the condition for the AND circuit U13 is met via the line M. and the write command is sent out over the line ES2, which then only becomes effective in the AND circuit U2, The In this case, the pending address is written into the address memory ASp2.

At the same time, the switching of the control switch SS 'is prepared, which then switches to the position s3 ^f with the next clock pulse Tst.In this position, stages 2 and 3 are marked via lines SA2 and SA3 and the AND circuits U15 and Ul6 are prepared . If no free line was found, will. transmit the write commands over the line ES2. The further search is then carried out in a corresponding manner.

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Claims (2)

K.Nigge - 6
Claims Arrangement for the transmission of information from a central unit to peripheral.Units with information storage, in particular for the route search in centrally controlled coupling networks of telecommunications, characterized in that an information transmitter (AK) is provided in the central unit (M), from which the respective information to all information memories (ASpI, 2, 3) of the peripheral units is transmitted that the information transmitter is switched on with a first clock (Tl) that with a second clock (T2) whose phase is shifted from the first clock by such a time that the transient processes for the transmitted information have ended, the result of the evaluation of the process initiated by the previous information is received and, depending on this, a write command is transmitted to all or a group of information memories, which is only effective in the information memories that are activated by one of a tax bill age (SS) emitted signal are marked that the control switch is controlled by a third clock (Tst), the pulses of which are emitted between those of the second (T2) and first clock (Tl), and that the switching in some positions directly by the third clock takes place and in the other positions only when the third clock and a certain return signal (M) from the peripheral units occur at the same time, 2. Arrangement according to claim I _1, characterized in that a write wire (ES) is provided which is connected in parallel to all information memories (ASpI ₁ 2, 3) and that the control switch (SS) marks one memory after the other, 509809/0525 - ίο - K. Nigge - 6 3. Arrangement according to claim 1, characterized in that two write-in cores (ESl ₁ 2) are provided, one of which ^{transmits the write-in command depending on the position of the control switch (SS 1} ) and the return signal (M, NM) that the Write-in wheels are alternately connected to the information memories (ASpI, 3; 2) and that the control switch (SS ') controls two consecutive information memories. 509809/0525 M. Blank