GB1447573A - Circuit arrangement for providing unipolar output signals - Google Patents
Circuit arrangement for providing unipolar output signalsInfo
- Publication number
- GB1447573A GB1447573A GB1552474A GB1552474A GB1447573A GB 1447573 A GB1447573 A GB 1447573A GB 1552474 A GB1552474 A GB 1552474A GB 1552474 A GB1552474 A GB 1552474A GB 1447573 A GB1447573 A GB 1447573A
- Authority
- GB
- United Kingdom
- Prior art keywords
- output
- trigger circuit
- input
- polarity
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/003—Changing the DC level
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electronic Switches (AREA)
Abstract
1447573 Transistor circuits KOMBINAT VEB FUNKWERK ERFURT 8 April 1974 15524/74 Heading H3T A circuit for converting bipolar input signals to unipolar output signals with simultaneous delivery of polarity information comprises: a delay network 3 and a trigger circuit 5 connected to input 1; an impedance converter 2 and a polarity inverter 4 connected to outputs from the delay network 3; gating circuits 6, 7 having their inputs connected to the outputs from the converter 2 and inverter 4 respectively and their output connected to a circuit output 9, the gates being controlled by respective control signal from the trigger circuit 5; and an output 10 for polarity information also connected to the trigger circuit 5. Input signals of one polarity set trigger circuit 5 to a first state in which gate 6 is open to pass the input at 1 to output 9 via impedance converter 2. Input signals of the other polarity cause trigger circuit 5 to open gate 8 to pass the input to the output via inverter 4. The outputs from the trigger circuit are fed to the gates via a control stage 7 (detailed in Fig. 2, not shown) which comprises two cascaded transistor stages in each control path (19, 21 or 20, 22) the output control signals being taken from the collectors of the second transistor of each pair and the emitters of these second transistors (21, 22) being coupled to a constant current source including a further transistor (23). The two gates comprise respective diode bridge circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1552474A GB1447573A (en) | 1974-04-08 | 1974-04-08 | Circuit arrangement for providing unipolar output signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1552474A GB1447573A (en) | 1974-04-08 | 1974-04-08 | Circuit arrangement for providing unipolar output signals |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1447573A true GB1447573A (en) | 1976-08-25 |
Family
ID=10060665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1552474A Expired GB1447573A (en) | 1974-04-08 | 1974-04-08 | Circuit arrangement for providing unipolar output signals |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1447573A (en) |
-
1974
- 1974-04-08 GB GB1552474A patent/GB1447573A/en not_active Expired
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |