GB1447297A - Data processing system - Google Patents

Data processing system

Info

Publication number
GB1447297A
GB1447297A GB5352173A GB5352173A GB1447297A GB 1447297 A GB1447297 A GB 1447297A GB 5352173 A GB5352173 A GB 5352173A GB 5352173 A GB5352173 A GB 5352173A GB 1447297 A GB1447297 A GB 1447297A
Authority
GB
United Kingdom
Prior art keywords
channel
address
store
logic
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5352173A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu IT Holdings Inc
Original Assignee
Fujitsu Ltd
Amdahl Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Amdahl Corp filed Critical Fujitsu Ltd
Publication of GB1447297A publication Critical patent/GB1447297A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Stored Programmes (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)
GB5352173A 1972-12-06 1973-11-19 Data processing system Expired GB1447297A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US31273372A 1972-12-06 1972-12-06

Publications (1)

Publication Number Publication Date
GB1447297A true GB1447297A (en) 1976-08-25

Family

ID=23212764

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5352173A Expired GB1447297A (en) 1972-12-06 1973-11-19 Data processing system

Country Status (15)

Country Link
JP (1) JPS5610655B2 (de)
AT (1) AT351302B (de)
AU (1) AU498489B2 (de)
BE (1) BE808257A (de)
BR (1) BR7309515D0 (de)
CA (1) CA1008563A (de)
CH (1) CH584427A5 (de)
DE (1) DE2360303C2 (de)
ES (1) ES421412A1 (de)
FR (1) FR2210309A5 (de)
GB (1) GB1447297A (de)
IT (1) IT1006675B (de)
NL (1) NL7316646A (de)
NO (1) NO141450C (de)
SE (1) SE402495B (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4403282A (en) 1978-01-23 1983-09-06 Data General Corporation Data processing system using a high speed data channel for providing direct memory access for block data transfers
WO1998006038A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Architectural support for software pipelining of loops
WO1998006039A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Disambiguation memory circuit and operating method

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7416631A (nl) * 1974-12-20 1976-06-22 Philips Nv Rekenmachinesysteem.
US3990051A (en) * 1975-03-26 1976-11-02 Honeywell Information Systems, Inc. Memory steering in a data processing system
JPS5922977B2 (ja) * 1975-06-30 1984-05-30 ハネイウエル・インフオメ−シヨン・システムスインコ−ポレ−テツド 入出力装置によるペ−ジメモリ呼び出し方法
JPS5325326A (en) * 1976-06-07 1978-03-09 Amdahl Corp Data processing system with plural channel processor
JPS533029A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533024A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533026A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533027A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533025A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS533028A (en) * 1976-06-30 1978-01-12 Toshiba Corp Electronic computer
JPS5322331A (en) * 1976-08-13 1978-03-01 Fujitsu Ltd Dynamic address conversion s ystem
DK157954C (da) * 1978-01-23 1990-08-13 Data General Corp Databehandlingsanlaeg med direkte lageradgang
JPS54129942A (en) * 1978-03-31 1979-10-08 Fujitsu Ltd Direct transfer system between sub-systems
DE2827745C2 (de) * 1978-06-23 1985-05-23 Fujitsu Ltd., Kawasaki, Kanagawa Dynamische Adressenübersetzungsanordnung
JPS6013501B2 (ja) * 1978-09-18 1985-04-08 富士通株式会社 仮想計算機システムにおけるチヤネルアドレス制御方式
JPS60120372A (ja) * 1983-12-02 1985-06-27 Matsushita Electric Ind Co Ltd カラ−画像形成装置
JPH0713869A (ja) * 1993-06-28 1995-01-17 Fujitsu Ltd 動的アドレス変換機能を持つデータ処理システム
JP4875965B2 (ja) * 2006-10-31 2012-02-15 久司 中川 素振り練習具

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE758815A (fr) * 1969-11-28 1971-04-16 Burroughs Corp Systeme de traitement d'information presentant des moyens pour la preparation dynamique d'adresses de memoire
US3647348A (en) * 1970-01-19 1972-03-07 Fairchild Camera Instr Co Hardware-oriented paging control system
FR10582E (fr) * 1970-06-29 1909-07-30 Paul Alexis Victor Lerolle Jeu de serrures avec passe-partout
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
JPS5232711B2 (de) * 1972-03-29 1977-08-23

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4403282A (en) 1978-01-23 1983-09-06 Data General Corporation Data processing system using a high speed data channel for providing direct memory access for block data transfers
WO1998006038A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Architectural support for software pipelining of loops
WO1998006039A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Disambiguation memory circuit and operating method
US5794029A (en) * 1996-08-07 1998-08-11 Elbrus International Ltd. Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor

Also Published As

Publication number Publication date
NO141450B (no) 1979-12-03
AU6305473A (en) 1975-05-29
ES421412A1 (es) 1976-07-16
CA1008563A (en) 1977-04-12
NL7316646A (de) 1974-06-10
CH584427A5 (de) 1977-01-31
AU498489B2 (en) 1979-03-15
NO141450C (no) 1980-03-12
BR7309515D0 (pt) 1974-08-29
SE402495B (sv) 1978-07-03
DE2360303C2 (de) 1983-12-15
FR2210309A5 (de) 1974-07-05
JPS5076950A (de) 1975-06-24
BE808257A (fr) 1974-03-29
IT1006675B (it) 1976-10-20
ATA1018173A (de) 1978-12-15
JPS5610655B2 (de) 1981-03-10
AT351302B (de) 1979-07-25
DE2360303A1 (de) 1974-06-20

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years

Effective date: 19931118