GB1444554A - Multilayer printed circuits - Google Patents
Multilayer printed circuitsInfo
- Publication number
- GB1444554A GB1444554A GB5800772A GB5800772A GB1444554A GB 1444554 A GB1444554 A GB 1444554A GB 5800772 A GB5800772 A GB 5800772A GB 5800772 A GB5800772 A GB 5800772A GB 1444554 A GB1444554 A GB 1444554A
- Authority
- GB
- United Kingdom
- Prior art keywords
- copper
- layers
- tracks
- extending
- stack
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0379—Stacked conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0397—Tab
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
1444554 Printed circuits DEFENCE SECRETARY OF STATE FOR 8 Jan 1974 [15 Dec 1972] 58007/72 Heading H1R A multilayer printed circuit board (Fig. 1) having edge interlayer connections comprises a stack of copper-polyester film layers 1 cemented to a glass fibre base board 2; components (not shown) being placed on the upper side of the stack with leads extending through insulated holes of the layers and soldered to copper tracks 3 on the underside extending to the edges of the board. Copper tabs 4 extending from the film layers are bent round the edges to solderably contact the tracks 3 for selective interconnection (Fig. 2). The tracks and tabs on the copper-polyester layers are defined by etching over masks. Copper screening planes may be inserted between layers, and the track/layer configuration may be computer derived.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB5800772A GB1444554A (en) | 1972-12-15 | 1972-12-15 | Multilayer printed circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB5800772A GB1444554A (en) | 1972-12-15 | 1972-12-15 | Multilayer printed circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1444554A true GB1444554A (en) | 1976-08-04 |
Family
ID=10480574
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5800772A Expired GB1444554A (en) | 1972-12-15 | 1972-12-15 | Multilayer printed circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1444554A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4164071A (en) * | 1977-12-27 | 1979-08-14 | Ford Motor Company | Method of forming a circuit board with integral terminals |
-
1972
- 1972-12-15 GB GB5800772A patent/GB1444554A/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4164071A (en) * | 1977-12-27 | 1979-08-14 | Ford Motor Company | Method of forming a circuit board with integral terminals |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |