GB1434041A - Data input/output devices - Google Patents

Abstract

1434041 Input/output device SIEMENS AG 3 July 1973 [4 July 1972] 31674/73 Heading G4A [Also in Division H4] An input/output device is arranged to control data transfers between one or more peripheral devices and a central unit in response to channel commands, the device being arranged inresponse to the appropriate commands to derive main store addresses for the transfers from the command and to receive such addresses from the peripherals. The device is shown connected between peripheral PE (several may be provided with priority resolution of simultaneous requests) and central unit ZE. In "normal" operation the device controls data transfers between the peripheral and locations in store ASP addressed in response to channel commands provided by the central unit and loaded in register BFR. Block transfers are controlled by commands specifying a zone in store ASP, the current transfer address, stored in register ADRR, being incremented or decremented until the transfer is complete. The device also operates in response to an appropriate channel command to transfer data to and from store locations addressed by the peripheral(s), in one of two modes. In the first mode the peripheral sends a transfer request PA and a store address on line DE, the address being loaded in register ADRR and a bit R is set to indicate receipt of the address. The device then transfers the contents of the addressed location to the peripheral via line DA. The peripheral then sends a second request PA together with data on line DE which is loaded in the addressed location. The data sent by the peripheral may be that received from the central unit for error check purposes. In the second mode the peripheral sends a request PA, and address DE, and a direction of transfer signal. For transfers to the peripheral the device sends an acknowledgement together with the contents of the addressed location. For transfers to the central unit the peripheral sends a subsequent request PA together with the data which is loaded into the addressed store location. Modifications are mentioned in which each transfer of data or addresses may require several transfer operations and in which the addresses sent by the peripheral are treated as an index to be added to a base to give the actual address. Furthermore following a central unit to peripheral transfer the store address may be maintained valid for a series of peripheral to central unit transfers which require no further address but which occur in response to corresponding request and direction signals from the peripheral.