GB1428704A - Data processing arrangements - Google Patents

Data processing arrangements

Info

Publication number
GB1428704A
GB1428704A GB1786673A GB1786673A GB1428704A GB 1428704 A GB1428704 A GB 1428704A GB 1786673 A GB1786673 A GB 1786673A GB 1786673 A GB1786673 A GB 1786673A GB 1428704 A GB1428704 A GB 1428704A
Authority
GB
United Kingdom
Prior art keywords
data
line
acceptor
acceptor line
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1786673A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Priority to GB1786673A priority Critical patent/GB1428704A/en
Publication of GB1428704A publication Critical patent/GB1428704A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4269—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a handshaking protocol, e.g. Centronics connection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Debugging And Monitoring (AREA)

Abstract

1428704 Data transmission INTERNATIONAL COMPUTERS Ltd 11 April 1974 [13 April 1973] 17866/73 Heading H4K In an arrangement comprising a first program controlled device, e.g. central processor, interconnected by an acceptor line, a source line and a data transfer-path to a second device, e.g. a subsidiary or second processing unit, to ensure that the first device is not held up waiting for the acceptor line to change state, the first device is programmed so that, when it has data to transfer, it periodically examines the acceptor line, continuing with the execution of a program sequence between such examinations, until it finds the acceptor line active, indicating that the second device is ready to receive data, whereupon the first device activates the source line, applies the data to the data path, and then continues with execution of the program sequence, periodically returning to examine the acceptor line to determine whether it has been deactivated, indicating acceptance of the data by the second device, in which case the first device deactivates the source line. Preferably the first device is further programmed so that, when it is ready to receive data, it activates a further acceptor line and then proceeds with execution of a program loop, periodically returning to examine a further source line to determine whether it is active, indicating that the second device is presenting data, in which case the first device reads the presented data from the data path and then deactivates said further acceptor line. In the programmed routine a parity check of received data is made and if incorrect the routine undergoes a further determined number of cycles after which transfer is abandoned and a warning indication given. Operation of the arrangement is described in detail in the Specification.
GB1786673A 1973-04-13 1973-04-13 Data processing arrangements Expired GB1428704A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1786673A GB1428704A (en) 1973-04-13 1973-04-13 Data processing arrangements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1786673A GB1428704A (en) 1973-04-13 1973-04-13 Data processing arrangements

Publications (1)

Publication Number Publication Date
GB1428704A true GB1428704A (en) 1976-03-17

Family

ID=10102592

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1786673A Expired GB1428704A (en) 1973-04-13 1973-04-13 Data processing arrangements

Country Status (1)

Country Link
GB (1) GB1428704A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2476352A1 (en) * 1979-10-30 1981-08-21 Pitney Bowes Inc ELECTRONIC POSTAGE MACHINE COMPRISING SEVERAL CALCULATION DEVICES
FR2483713A1 (en) * 1980-05-30 1981-12-04 Cii Honeywell Bull DEVICE FOR TRANSMITTING SIGNALS BETWEEN TWO INFORMATION PROCESSING STATIONS
EP0048662A1 (en) * 1980-09-16 1982-03-31 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Coupler for removable electronic carriers
US4422148A (en) 1979-10-30 1983-12-20 Pitney Bowes Inc. Electronic postage meter having plural computing systems
US4498187A (en) * 1979-10-30 1985-02-05 Pitney Bowes Inc. Electronic postage meter having plural computing systems
US4525785A (en) * 1979-10-30 1985-06-25 Pitney Bowes Inc. Electronic postage meter having plural computing system
US4607328A (en) * 1981-08-24 1986-08-19 Sony Corporation Data transfer apparatus for a microcomputer system
CN100373299C (en) * 2004-09-30 2008-03-05 因芬尼昂技术股份公司 Method for controlling data communication between two processor and bi-processor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2476352A1 (en) * 1979-10-30 1981-08-21 Pitney Bowes Inc ELECTRONIC POSTAGE MACHINE COMPRISING SEVERAL CALCULATION DEVICES
US4422148A (en) 1979-10-30 1983-12-20 Pitney Bowes Inc. Electronic postage meter having plural computing systems
US4498187A (en) * 1979-10-30 1985-02-05 Pitney Bowes Inc. Electronic postage meter having plural computing systems
US4525785A (en) * 1979-10-30 1985-06-25 Pitney Bowes Inc. Electronic postage meter having plural computing system
FR2483713A1 (en) * 1980-05-30 1981-12-04 Cii Honeywell Bull DEVICE FOR TRANSMITTING SIGNALS BETWEEN TWO INFORMATION PROCESSING STATIONS
EP0048662A1 (en) * 1980-09-16 1982-03-31 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Coupler for removable electronic carriers
US4607328A (en) * 1981-08-24 1986-08-19 Sony Corporation Data transfer apparatus for a microcomputer system
CN100373299C (en) * 2004-09-30 2008-03-05 因芬尼昂技术股份公司 Method for controlling data communication between two processor and bi-processor device
US7467312B2 (en) 2004-09-30 2008-12-16 Infineon Technologies Ag Arrangement and method for controlling communication of data between processors

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years

Effective date: 19940410