GB1419970A - Field effect transistor memory circuits - Google Patents

Abstract

1419970 FET data stores SONY CORP 28 Dec 1972 [29 Dec 1971] 59898/72 Heading H3T A variable threshold F.E.T. 2, 5, 8 or 11 can be set/reset by a single input terminal R/W only when its source is earthed through an X- selection F.E.T. 1, 4, 7 or 10 and a Y-selection F.E.T. 17 or 18. The arrangement is said to require the necessary high voltages for threshold-setting to be applied to only one terminal (i.e. R/W), permitting the memory and addressing F.E.T.s to be formed on a single chip. If for example F.E.T.s 1 and 17 are turned on by X1, Y1 then F.E.T. 2 can have its threshold set to the high state (1) by +40 volts at R/W, this state requiring a gate voltage of + 15 v. (Fig. 4, not shown) to make F.E.T. 2 conduct during a subsequent read period. Thus a + 10 v. read signal at R/W produces conduction of F.E.T. 2 only if the low threshold exists (0). To reset the low threshold, R/W goes to - 40 v. while X1 and Y1 select F.E.T. 2, and while another F.E.T. 13 is turned on by an erase signal E to earth the drain of F.E.T. 2. Conduction of F.E.T. 2 during reading is detected at R OUT <SP>1</SP>, and similarly for F.E.T. 5. For F.E.T.s 8 and 11, readout to R OUT <SP>1</SP> requires gating F.E.T.s 15 and 16 to be turned on by a read signal R. In one modification, a single load F.E.T. 3,6 (Fig. 5, not shown) is used for each column, being connected to each cell by extra gating F.E.T.s (31, 32; 35, 36; &c.) controlled by complements of the X, Y signals and by the read signal R. In another modification (Fig. 7, not shown), the erase and read F.E.T.s 14, 15, 16 are removed, the X select F.E.T.s 1, 4, 7, 10 and their respective variable threshold F.E.T.s 2, 5, 8, 11 exchange positions, and the Y select F.E.T.s 17, 18 are connected to receive the read signal R instead of earth. The variable threshold F.E.T.s may use silicon nitride, or aluminium oxide, between the gate and the silicon oxide layer.