JPS5443634A - Memory erasing method - Google Patents

Memory erasing method

Info

Publication number
JPS5443634A
JPS5443634A JP11027077A JP11027077A JPS5443634A JP S5443634 A JPS5443634 A JP S5443634A JP 11027077 A JP11027077 A JP 11027077A JP 11027077 A JP11027077 A JP 11027077A JP S5443634 A JPS5443634 A JP S5443634A
Authority
JP
Japan
Prior art keywords
memory
erasing
power supply
fixed time
erasing voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11027077A
Other languages
Japanese (ja)
Other versions
JPS5744996B2 (en
Inventor
Takeshi Mizusawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11027077A priority Critical patent/JPS5443634A/en
Publication of JPS5443634A publication Critical patent/JPS5443634A/en
Publication of JPS5744996B2 publication Critical patent/JPS5744996B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Abstract

PURPOSE:Several memory integrated-circuits are grouped into one or more, one common erasing power supply is connected to each group via a switching method, and an erasing voltage is applied while giving a fixed time delay to each group, thereby erasing several memories in a short time with a small-capacity power supply. CONSTITUTION:Applying an erasing voltage avalanche-injects memory erasing charge into memory cells, thereby erasing memory contents. In this method mentioned above, the memory of the integrated-circuit is divided into memory groups M1, M2...Mn which power supply PS is able to supply an erasing voltage. Then, power supply PS is connected via relay contacts C1, C2...Cn which correspond to memory groups M1, M2...Mn respectively. Those relay contacts C1, C2...Cn are closed by connection control circuit CK being delayed respectively by a fixed time, thereby applying sequentially an erasing voltage to memory groups M1, M2...Mn with a fixed time difference.
JP11027077A 1977-09-13 1977-09-13 Memory erasing method Granted JPS5443634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11027077A JPS5443634A (en) 1977-09-13 1977-09-13 Memory erasing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11027077A JPS5443634A (en) 1977-09-13 1977-09-13 Memory erasing method

Publications (2)

Publication Number Publication Date
JPS5443634A true JPS5443634A (en) 1979-04-06
JPS5744996B2 JPS5744996B2 (en) 1982-09-25

Family

ID=14531418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11027077A Granted JPS5443634A (en) 1977-09-13 1977-09-13 Memory erasing method

Country Status (1)

Country Link
JP (1) JPS5443634A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474073B1 (en) * 1997-11-28 2005-06-29 주식회사 하이닉스반도체 Flash memory device and its data erasing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS644899U (en) * 1987-06-26 1989-01-12

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4874128A (en) * 1971-12-29 1973-10-05
JPS50109636A (en) * 1974-01-29 1975-08-28

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4874128A (en) * 1971-12-29 1973-10-05
JPS50109636A (en) * 1974-01-29 1975-08-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474073B1 (en) * 1997-11-28 2005-06-29 주식회사 하이닉스반도체 Flash memory device and its data erasing method

Also Published As

Publication number Publication date
JPS5744996B2 (en) 1982-09-25

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