GB1393123A - Semiconductor device manufacture - Google Patents
Semiconductor device manufactureInfo
- Publication number
- GB1393123A GB1393123A GB2370072A GB2370072A GB1393123A GB 1393123 A GB1393123 A GB 1393123A GB 2370072 A GB2370072 A GB 2370072A GB 2370072 A GB2370072 A GB 2370072A GB 1393123 A GB1393123 A GB 1393123A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- zones
- type
- insulant
- zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
- H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
- H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
Landscapes
- Element Separation (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL7107039.A NL166156C (nl) | 1971-05-22 | 1971-05-22 | Halfgeleiderinrichting bevattende ten minste een op een halfgeleidersubstraatlichaam aangebrachte halfge- leiderlaag met ten minste een isolatiezone, welke een in de halfgeleiderlaag verzonken isolatielaag uit door plaatselijke thermische oxydatie van het half- geleidermateriaal van de halfgeleiderlaag gevormd isolerend materiaal bevat en een werkwijze voor het vervaardigen daarvan. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1393123A true GB1393123A (en) | 1975-05-07 |
Family
ID=19813232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB2370072A Expired GB1393123A (en) | 1971-05-22 | 1972-05-19 | Semiconductor device manufacture |
Country Status (16)
| Country | Link |
|---|---|
| US (1) | US4272776A (https=) |
| JP (3) | JPS5236394B1 (https=) |
| AR (1) | AR193866A1 (https=) |
| AT (1) | AT341000B (https=) |
| AU (1) | AU473149B2 (https=) |
| BE (1) | BE783737A (https=) |
| BR (1) | BR7203232D0 (https=) |
| CA (1) | CA975467A (https=) |
| CH (1) | CH555088A (https=) |
| DE (1) | DE2224634C2 (https=) |
| ES (2) | ES403027A1 (https=) |
| FR (1) | FR2138904B1 (https=) |
| GB (1) | GB1393123A (https=) |
| IT (1) | IT955675B (https=) |
| NL (1) | NL166156C (https=) |
| SE (1) | SE382281B (https=) |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4396933A (en) * | 1971-06-18 | 1983-08-02 | International Business Machines Corporation | Dielectrically isolated semiconductor devices |
| US3955269A (en) * | 1975-06-19 | 1976-05-11 | International Business Machines Corporation | Fabricating high performance integrated bipolar and complementary field effect transistors |
| US3961999A (en) * | 1975-06-30 | 1976-06-08 | Ibm Corporation | Method for forming recessed dielectric isolation with a minimized "bird's beak" problem |
| FR2408914A1 (fr) * | 1977-11-14 | 1979-06-08 | Radiotechnique Compelec | Dispositif semi-conducteur monolithique comprenant deux transistors complementaires et son procede de fabrication |
| JPS54142688A (en) * | 1978-04-28 | 1979-11-07 | Shimada Burasuto Kougiyou Kk | Inner surface machining method and device of pipe |
| US4238278A (en) * | 1979-06-14 | 1980-12-09 | International Business Machines Corporation | Polycrystalline silicon oxidation method for making shallow and deep isolation trenches |
| USRE32090E (en) * | 1980-05-07 | 1986-03-04 | At&T Bell Laboratories | Silicon integrated circuits |
| US4353086A (en) * | 1980-05-07 | 1982-10-05 | Bell Telephone Laboratories, Incorporated | Silicon integrated circuits |
| US4467312A (en) * | 1980-12-23 | 1984-08-21 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor resistor device |
| GB2104722B (en) * | 1981-06-25 | 1985-04-24 | Suwa Seikosha Kk | Mos semiconductor device and method of manufacturing the same |
| NL8203323A (nl) * | 1982-08-25 | 1984-03-16 | Philips Nv | Geintegreerde weerstand. |
| US4637125A (en) * | 1983-09-22 | 1987-01-20 | Kabushiki Kaisha Toshiba | Method for making a semiconductor integrated device including bipolar transistor and CMOS transistor |
| US4574469A (en) * | 1984-09-14 | 1986-03-11 | Motorola, Inc. | Process for self-aligned buried layer, channel-stop, and isolation |
| US4583282A (en) * | 1984-09-14 | 1986-04-22 | Motorola, Inc. | Process for self-aligned buried layer, field guard, and isolation |
| JPH0779133B2 (ja) * | 1986-06-12 | 1995-08-23 | 松下電器産業株式会社 | 半導体装置の製造方法 |
| US5023690A (en) * | 1986-10-24 | 1991-06-11 | Texas Instruments Incorporated | Merged bipolar and complementary metal oxide semiconductor transistor device |
| US4737468A (en) * | 1987-04-13 | 1988-04-12 | Motorola Inc. | Process for developing implanted buried layer and/or key locators |
| US4951115A (en) * | 1989-03-06 | 1990-08-21 | International Business Machines Corp. | Complementary transistor structure and method for manufacture |
| US5139966A (en) * | 1990-04-02 | 1992-08-18 | National Semiconductor Corporation | Low resistance silicided substrate contact |
| JPH04112565A (ja) * | 1990-08-31 | 1992-04-14 | Nec Corp | 半導体抵抗素子及びその製造方法 |
| US5504363A (en) * | 1992-09-02 | 1996-04-02 | Motorola Inc. | Semiconductor device |
| EP1801855B1 (en) * | 2005-12-22 | 2009-01-14 | Freiberger Compound Materials GmbH | Processes for selective masking of III-N layers and for the preparation of free-standing III-N layers or of devices |
| US7691734B2 (en) * | 2007-03-01 | 2010-04-06 | International Business Machines Corporation | Deep trench based far subcollector reachthrough |
| DE102007029756A1 (de) * | 2007-06-27 | 2009-01-02 | X-Fab Semiconductor Foundries Ag | Halbleiterstruktur zur Herstellung eines Trägerwaferkontaktes in grabenisolierten SOI-Scheiben |
| US9176173B2 (en) * | 2011-11-28 | 2015-11-03 | Texas Instruments Incorporated | Method for detecting imperfect mounting of a rod-shaped metallic object in a metallic hollow shaft and a device |
| KR101874586B1 (ko) * | 2012-08-06 | 2018-07-04 | 삼성전자주식회사 | 포토키를 이용한 반도체 소자의 제조 방법 |
| US20190305128A1 (en) * | 2018-04-03 | 2019-10-03 | Vanguard International Semiconductor Corporation | Semiconductor structure and method for forming the same |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3461003A (en) * | 1964-12-14 | 1969-08-12 | Motorola Inc | Method of fabricating a semiconductor structure with an electrically isolated region of semiconductor material |
| US3372063A (en) * | 1964-12-22 | 1968-03-05 | Hitachi Ltd | Method for manufacturing at least one electrically isolated region of a semiconductive material |
| US3598664A (en) * | 1964-12-29 | 1971-08-10 | Texas Instruments Inc | High frequency transistor and process for fabricating same |
| US3386865A (en) * | 1965-05-10 | 1968-06-04 | Ibm | Process of making planar semiconductor devices isolated by encapsulating oxide filled channels |
| US3534234A (en) * | 1966-12-15 | 1970-10-13 | Texas Instruments Inc | Modified planar process for making semiconductor devices having ultrafine mesa type geometry |
| FR1527898A (fr) * | 1967-03-16 | 1968-06-07 | Radiotechnique Coprim Rtc | Agencement de dispositifs semi-conducteurs portés par un support commun et son procédé de fabrication |
| US3432792A (en) * | 1967-08-03 | 1969-03-11 | Teledyne Inc | Isolated resistor for integrated circuit |
| GB1206308A (en) * | 1967-11-22 | 1970-09-23 | Sony Corp | Method of making semiconductor wafer |
| US3617822A (en) * | 1967-12-05 | 1971-11-02 | Sony Corp | Semiconductor integrated circuit |
| FR1601776A (fr) * | 1967-12-05 | 1970-09-14 | Sony Corp | Procédé de fabrication de circuits semi-conducteurs intégrés et circuits ainsi obtenus |
| US3649386A (en) * | 1968-04-23 | 1972-03-14 | Bell Telephone Labor Inc | Method of fabricating semiconductor devices |
| US3648128A (en) * | 1968-05-25 | 1972-03-07 | Sony Corp | An integrated complementary transistor circuit chip with polycrystalline contact to buried collector regions |
| US3702790A (en) * | 1968-12-02 | 1972-11-14 | Nippon Electric Co | Monolithic integrated circuit device and method of manufacturing the same |
| US3659162A (en) * | 1968-12-27 | 1972-04-25 | Nippon Electric Co | Semiconductor integrated circuit device having improved wiring layer structure |
| US3621346A (en) * | 1970-01-28 | 1971-11-16 | Ibm | Process for forming semiconductor devices with polycrystalline diffusion pathways and devices formed thereby |
| US3703420A (en) * | 1970-03-03 | 1972-11-21 | Ibm | Lateral transistor structure and process for forming the same |
| US3657612A (en) * | 1970-04-20 | 1972-04-18 | Ibm | Inverse transistor with high current gain |
| US3865624A (en) * | 1970-06-29 | 1975-02-11 | Bell Telephone Labor Inc | Interconnection of electrical devices |
| NL169936C (nl) * | 1970-07-10 | 1982-09-01 | Philips Nv | Halfgeleiderinrichting omvattende een halfgeleiderlichaam met een althans ten dele in het halfgeleiderlichaam verzonken oxydepatroon. |
| US3736193A (en) * | 1970-10-26 | 1973-05-29 | Fairchild Camera Instr Co | Single crystal-polycrystalline process for electrical isolation in integrated circuits |
| US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
| US3796613A (en) * | 1971-06-18 | 1974-03-12 | Ibm | Method of forming dielectric isolation for high density pedestal semiconductor devices |
| GB1516304A (en) * | 1974-07-25 | 1978-07-05 | Dunlop Ltd | Outflow meter |
-
1971
- 1971-05-22 NL NL7107039.A patent/NL166156C/xx not_active IP Right Cessation
-
1972
- 1972-05-17 CA CA142,386A patent/CA975467A/en not_active Expired
- 1972-05-18 AU AU42414/72A patent/AU473149B2/en not_active Expired
- 1972-05-18 US US05/254,604 patent/US4272776A/en not_active Expired - Lifetime
- 1972-05-19 GB GB2370072A patent/GB1393123A/en not_active Expired
- 1972-05-19 BE BE783737A patent/BE783737A/xx not_active IP Right Cessation
- 1972-05-19 AT AT439472A patent/AT341000B/de not_active IP Right Cessation
- 1972-05-19 SE SE7206614A patent/SE382281B/xx unknown
- 1972-05-19 IT IT24612/72A patent/IT955675B/it active
- 1972-05-19 CH CH753372A patent/CH555088A/xx not_active IP Right Cessation
- 1972-05-19 DE DE2224634A patent/DE2224634C2/de not_active Expired
- 1972-05-20 ES ES403027A patent/ES403027A1/es not_active Expired
- 1972-05-22 BR BR3232/72A patent/BR7203232D0/pt unknown
- 1972-05-22 JP JP47049965A patent/JPS5236394B1/ja active Pending
- 1972-05-22 AR AR242127A patent/AR193866A1/es active
- 1972-05-23 FR FR7218312A patent/FR2138904B1/fr not_active Expired
-
1973
- 1973-08-06 ES ES417610A patent/ES417610A1/es not_active Expired
-
1977
- 1977-04-20 JP JP4463477A patent/JPS52144984A/ja active Pending
- 1977-04-20 JP JP4463577A patent/JPS52144985A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US4272776A (en) | 1981-06-09 |
| DE2224634A1 (de) | 1972-11-30 |
| IT955675B (it) | 1973-09-29 |
| FR2138904B1 (https=) | 1980-04-04 |
| FR2138904A1 (https=) | 1973-01-05 |
| DE2224634C2 (de) | 1982-04-22 |
| CA975467A (en) | 1975-09-30 |
| JPS52144985A (en) | 1977-12-02 |
| JPS5236394B1 (https=) | 1977-09-14 |
| AU473149B2 (en) | 1976-06-17 |
| BE783737A (fr) | 1972-11-20 |
| JPS52144984A (en) | 1977-12-02 |
| CH555088A (de) | 1974-10-15 |
| NL7107039A (https=) | 1972-11-24 |
| BR7203232D0 (pt) | 1973-08-09 |
| AT341000B (de) | 1978-01-10 |
| ATA439472A (de) | 1977-05-15 |
| ES417610A1 (es) | 1976-06-16 |
| AR193866A1 (es) | 1973-05-31 |
| SE382281B (sv) | 1976-01-19 |
| ES403027A1 (es) | 1975-04-16 |
| NL166156B (nl) | 1981-01-15 |
| NL166156C (nl) | 1981-06-15 |
| AU4241472A (en) | 1973-11-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB1393123A (en) | Semiconductor device manufacture | |
| US4504332A (en) | Method of making a bipolar transistor | |
| US3947299A (en) | Method of manufacturing semiconductor devices | |
| US3524113A (en) | Complementary pnp-npn transistors and fabrication method therefor | |
| US3878552A (en) | Bipolar integrated circuit and method | |
| GB1421212A (en) | Semiconductor device manufacture | |
| GB1306817A (en) | Semiconductor devices | |
| US4008107A (en) | Method of manufacturing semiconductor devices with local oxidation of silicon surface | |
| US3911471A (en) | Semiconductor device and method of manufacturing same | |
| US4903109A (en) | Semiconductor devices having local oxide isolation | |
| GB1339095A (en) | Fabrication of monolithic integrated circuits | |
| US3956033A (en) | Method of fabricating an integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector | |
| US5198692A (en) | Semiconductor device including bipolar transistor with step impurity profile having low and high concentration emitter regions | |
| US3928091A (en) | Method for manufacturing a semiconductor device utilizing selective oxidation | |
| US4005453A (en) | Semiconductor device with isolated circuit elements and method of making | |
| EP0029552A2 (en) | Method for producing a semiconductor device | |
| EP0153686A2 (en) | Method for making transistor | |
| GB1310412A (en) | Semiconductor devices | |
| JPS63200568A (ja) | Cmos技術を用いたバイポーラ・トランジスタとその製造方法 | |
| US3909318A (en) | Method of forming complementary devices utilizing outdiffusion and selective oxidation | |
| GB1420676A (en) | Semiconductor devices | |
| US4132573A (en) | Method of manufacturing a monolithic integrated circuit utilizing epitaxial deposition and simultaneous outdiffusion | |
| GB1241057A (en) | Improvements relating to semiconductor structures | |
| US3974516A (en) | Method of manufacturing a semiconductor device having at least one insulated gate field effect transistor, and semiconductor device manufactured by using the method | |
| US4058825A (en) | Complementary transistor structure having two epitaxial layers and method of manufacturing same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |