GB1390385A - Variable length arithmetic unit - Google Patents

Variable length arithmetic unit

Info

Publication number
GB1390385A
GB1390385A GB2784272A GB2784272A GB1390385A GB 1390385 A GB1390385 A GB 1390385A GB 2784272 A GB2784272 A GB 2784272A GB 2784272 A GB2784272 A GB 2784272A GB 1390385 A GB1390385 A GB 1390385A
Authority
GB
United Kingdom
Prior art keywords
carry
adder
binary
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2784272A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of GB1390385A publication Critical patent/GB1390385A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3868—Bypass control, i.e. possibility to transfer an operand unchanged to the output
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
GB2784272A 1971-06-28 1972-06-14 Variable length arithmetic unit Expired GB1390385A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15709171A 1971-06-28 1971-06-28

Publications (1)

Publication Number Publication Date
GB1390385A true GB1390385A (en) 1975-04-09

Family

ID=22562302

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2784272A Expired GB1390385A (en) 1971-06-28 1972-06-14 Variable length arithmetic unit

Country Status (6)

Country Link
US (1) US3751650A (enExample)
JP (1) JPS5547416B1 (enExample)
BE (1) BE784858A (enExample)
DE (1) DE2230188C2 (enExample)
FR (1) FR2144306A5 (enExample)
GB (1) GB1390385A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112650469A (zh) * 2019-10-11 2021-04-13 意法半导体(格勒诺布尔2)公司 用于二进制标志确定的电路和方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3978456A (en) * 1974-12-16 1976-08-31 Bell Telephone Laboratories, Incorporated Byte-by-byte type processor circuit
US3987291A (en) * 1975-05-01 1976-10-19 International Business Machines Corporation Parallel digital arithmetic device having a variable number of independent arithmetic zones of variable width and location
US4021655A (en) * 1976-03-30 1977-05-03 International Business Machines Corporation Oversized data detection hardware for data processors which store data at variable length destinations
US4093982A (en) * 1976-05-03 1978-06-06 International Business Machines Corporation Microprocessor system
US4161784A (en) * 1978-01-05 1979-07-17 Honeywell Information Systems, Inc. Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands
GB2039104B (en) * 1979-01-02 1983-09-01 Honeywell Inf Systems Data processing system
US4454589A (en) * 1982-03-12 1984-06-12 The Unite States of America as represented by the Secretary of the Air Force Programmable arithmetic logic unit
US4785393A (en) * 1984-07-09 1988-11-15 Advanced Micro Devices, Inc. 32-Bit extended function arithmetic-logic unit on a single chip
EP0177268B1 (en) * 1984-10-01 1990-07-11 Unisys Corporation Programmable data path width in a programmable unit having plural levels of subinstructions sets
EP0333235A3 (en) * 1984-10-01 1989-11-23 Unisys Corporation Programmable data path width in a programmable unit having plural levels of subinstructions sets
JPH07113884B2 (ja) * 1985-12-28 1995-12-06 株式会社東芝 論理回路
US4866656A (en) * 1986-12-05 1989-09-12 American Telephone And Telegraph Company, At&T Bell Laboratories High-speed binary and decimal arithmetic logic unit
US5251164A (en) * 1992-05-22 1993-10-05 S-Mos Systems, Inc. Low-power area-efficient absolute value arithmetic unit
GB2270400B (en) * 1992-09-08 1996-09-18 Sony Corp Digital audio mixer
JP4147423B2 (ja) * 2004-11-12 2008-09-10 セイコーエプソン株式会社 任意精度演算器、任意精度演算方法、および電子機器
US8495114B1 (en) * 2005-05-23 2013-07-23 The Mathworks, Inc. System and methods for determining attributes for arithmetic operations with fixed-point numbers
US8484262B1 (en) 2005-12-22 2013-07-09 The Mathworks, Inc. System and methods for determining attributes for arithmetic operations with fixed-point numbers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2981471A (en) * 1957-12-09 1961-04-25 Honeywell Regulator Co Information manipulating apparatus
US3260840A (en) * 1961-12-28 1966-07-12 Ibm Variable mode arithmetic circuits with carry select
GB1054725A (enExample) * 1964-04-06
US3440412A (en) * 1965-12-20 1969-04-22 Sylvania Electric Prod Transistor logic circuits employed in a high speed adder
US3465133A (en) * 1966-06-07 1969-09-02 North American Rockwell Carry or borrow system for arithmetic computations
GB1145676A (en) * 1966-09-28 1969-03-19 Nippon Electric Co High speed adder circuit
US3535502A (en) * 1967-11-15 1970-10-20 Ibm Multiple input binary adder
GB1245441A (en) * 1968-08-27 1971-09-08 Int Computers Ltd Improvements in or relating to adders operating on variable fields within words

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112650469A (zh) * 2019-10-11 2021-04-13 意法半导体(格勒诺布尔2)公司 用于二进制标志确定的电路和方法

Also Published As

Publication number Publication date
BE784858A (fr) 1972-10-02
DE2230188A1 (de) 1973-01-11
US3751650A (en) 1973-08-07
FR2144306A5 (enExample) 1973-02-09
JPS5547416B1 (enExample) 1980-11-29
DE2230188C2 (de) 1986-07-17

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee