GB1373784A - Circuit arrangements for the regeneration of pulse-shaped signals - Google Patents
Circuit arrangements for the regeneration of pulse-shaped signalsInfo
- Publication number
- GB1373784A GB1373784A GB4686071A GB4686071A GB1373784A GB 1373784 A GB1373784 A GB 1373784A GB 4686071 A GB4686071 A GB 4686071A GB 4686071 A GB4686071 A GB 4686071A GB 1373784 A GB1373784 A GB 1373784A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pulse
- circuit
- pulses
- output
- waveform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/24—Relay circuits using discharge tubes or semiconductor devices
- H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
1373784 Pulse regenerators SIEMENS AG 8 Oct 1971 [30 Oct 1970] 46860/71 Heading H3P Pulses occurring in periodic time slots are regenerated by integrating the pulse during each slot, monitoring the output of the integrator to determine the identity of the pulse and using the output of the monitor to set a bistable circuit upon the occurrence of a timing pulse. In Fig. 1 the incoming pulses are integrated by circuit RC during each time slot and the integrator is reset by contact K at the end of the slot. The monitoring circuit W detects whether the output of the integrator has risen above a given value and sets correspondingly a bi-stable circuit F in response to a timing pulse occurring at the end of the slot. As described, the incoming pulses are bipolar and the circuit detects whether the pulse is positive or negative of zero. Fig. 7 receives signals in which successive "1" signals are represented by pulses of opposite polarity and a "0" is represented by a zero signal (Fig. 8g). These signals are continuously integrated by a circuit R-C to provide waveform 8h. Monitor W_ detects whether this waveform is above or below a threshold value, providing waveform 8i and this sets a bi-stable circuit in response to clock pulses k to produce an output waveform 81. The original data can be recovered from this by a pulseshaper P.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19702053378 DE2053378C3 (en) | 1970-10-30 | 1970-10-30 | Circuit arrangement for the regeneration of quasiternary pulse code modulated signals |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1373784A true GB1373784A (en) | 1974-11-13 |
Family
ID=5786673
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4686071A Expired GB1373784A (en) | 1970-10-30 | 1971-10-08 | Circuit arrangements for the regeneration of pulse-shaped signals |
Country Status (9)
Country | Link |
---|---|
AT (1) | AT313371B (en) |
AU (1) | AU463546B2 (en) |
BE (1) | BE774708A (en) |
CH (1) | CH547579A (en) |
DE (1) | DE2053378C3 (en) |
FR (1) | FR2113297A5 (en) |
GB (1) | GB1373784A (en) |
NL (1) | NL163931C (en) |
SE (1) | SE375675B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2268398A1 (en) * | 1974-04-19 | 1975-11-14 | Lignes Telegraph Telephon | Pulse shaping or regeneration circuit - uses a Schmitt trigger and memory with two parallel networks |
DE19857396C2 (en) * | 1998-12-12 | 2002-11-14 | Josef Von Stackelberg | Fail-safe binary comparator with ternary result and status display |
-
1970
- 1970-10-30 DE DE19702053378 patent/DE2053378C3/en not_active Expired
-
1971
- 1971-10-05 AT AT859171A patent/AT313371B/en not_active IP Right Cessation
- 1971-10-08 GB GB4686071A patent/GB1373784A/en not_active Expired
- 1971-10-20 AU AU34787/71A patent/AU463546B2/en not_active Expired
- 1971-10-21 NL NL7114492A patent/NL163931C/en active
- 1971-10-27 FR FR7138554A patent/FR2113297A5/fr not_active Expired
- 1971-10-28 CH CH547579D patent/CH547579A/en not_active IP Right Cessation
- 1971-10-29 BE BE774708A patent/BE774708A/en unknown
- 1971-10-29 SE SE1378371A patent/SE375675B/xx unknown
Also Published As
Publication number | Publication date |
---|---|
DE2053378C3 (en) | 1975-06-12 |
AU463546B2 (en) | 1975-07-31 |
DE2053378B2 (en) | 1974-10-24 |
NL163931C (en) | 1980-10-15 |
NL163931B (en) | 1980-05-16 |
SE375675B (en) | 1975-04-21 |
BE774708A (en) | 1972-02-14 |
DE2053378A1 (en) | 1972-05-04 |
FR2113297A5 (en) | 1972-06-23 |
AU3478771A (en) | 1973-05-03 |
NL7114492A (en) | 1972-05-03 |
CH547579A (en) | 1974-03-29 |
AT313371B (en) | 1974-02-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |