GB1368962A - Data processing apparatus - Google Patents

Data processing apparatus

Info

Publication number
GB1368962A
GB1368962A GB5618970A GB5618970A GB1368962A GB 1368962 A GB1368962 A GB 1368962A GB 5618970 A GB5618970 A GB 5618970A GB 5618970 A GB5618970 A GB 5618970A GB 1368962 A GB1368962 A GB 1368962A
Authority
GB
United Kingdom
Prior art keywords
driven
cells
clock pulses
common clock
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5618970A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Group Services Ltd
Original Assignee
Sperry Rand Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Ltd filed Critical Sperry Rand Ltd
Priority to GB5618970A priority Critical patent/GB1368962A/en
Priority to US00199955A priority patent/US3753241A/en
Priority to DE2157515A priority patent/DE2157515C3/de
Priority to IT54327/71A priority patent/IT945136B/it
Priority to FR7142219A priority patent/FR2115397B1/fr
Publication of GB1368962A publication Critical patent/GB1368962A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/007—Digital input from or digital output to memories of the shift register type

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Position, Course, Altitude, Or Attitude Of Moving Bodies (AREA)
GB5618970A 1970-11-26 1970-11-26 Data processing apparatus Expired GB1368962A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
GB5618970A GB1368962A (en) 1970-11-26 1970-11-26 Data processing apparatus
US00199955A US3753241A (en) 1970-11-26 1971-11-18 Shift register having internal buffer
DE2157515A DE2157515C3 (de) 1970-11-26 1971-11-19 Digitale Datenverarbeitungs-Einrichtung
IT54327/71A IT945136B (it) 1970-11-26 1971-11-24 Perfezionamento negli elaboratori di dati numerici
FR7142219A FR2115397B1 (enExample) 1970-11-26 1971-11-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5618970A GB1368962A (en) 1970-11-26 1970-11-26 Data processing apparatus

Publications (1)

Publication Number Publication Date
GB1368962A true GB1368962A (en) 1974-10-02

Family

ID=10475978

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5618970A Expired GB1368962A (en) 1970-11-26 1970-11-26 Data processing apparatus

Country Status (5)

Country Link
US (1) US3753241A (enExample)
DE (1) DE2157515C3 (enExample)
FR (1) FR2115397B1 (enExample)
GB (1) GB1368962A (enExample)
IT (1) IT945136B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409671A (en) * 1978-09-05 1983-10-11 Motorola, Inc. Data processor having single clock pin
JPS5916053A (ja) * 1982-07-16 1984-01-27 Nec Corp パイプライン演算装置
US4949249A (en) * 1987-04-10 1990-08-14 Prime Computer, Inc. Clock skew avoidance technique for pipeline processors
US4879718A (en) * 1987-11-30 1989-11-07 Tandem Computers Incorporated Scan data path coupling
US5293626A (en) * 1990-06-08 1994-03-08 Cray Research, Inc. Clock distribution apparatus and processes particularly useful in multiprocessor systems
JPH0520887A (ja) * 1990-11-21 1993-01-29 Nippon Steel Corp シフト回路及びシフトレジスタ
JPH0512157A (ja) * 1991-06-29 1993-01-22 Nec Corp シリアルデータ伝送装置
US6441666B1 (en) 2000-07-20 2002-08-27 Silicon Graphics, Inc. System and method for generating clock signals

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3398403A (en) * 1958-04-21 1968-08-20 Bell Telephone Labor Inc Data processing circuit
US3274566A (en) * 1966-02-15 1966-09-20 Rca Corp Storage circuit
US3543243A (en) * 1967-09-13 1970-11-24 Bell Telephone Labor Inc Data receiving arrangement
US3593298A (en) * 1970-02-19 1971-07-13 Burroughs Corp Digital storage system having a dual-function segmented register
US3670179A (en) * 1970-10-22 1972-06-13 Rca Corp Electrical circuit

Also Published As

Publication number Publication date
DE2157515A1 (de) 1972-05-31
DE2157515C3 (de) 1982-01-21
IT945136B (it) 1973-05-10
FR2115397B1 (enExample) 1976-09-03
DE2157515B2 (de) 1981-05-27
US3753241A (en) 1973-08-14
FR2115397A1 (enExample) 1972-07-07

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee