GB1367225A - Semiconductor device mounting arrangement - Google Patents

Semiconductor device mounting arrangement

Info

Publication number
GB1367225A
GB1367225A GB3401872A GB3401872A GB1367225A GB 1367225 A GB1367225 A GB 1367225A GB 3401872 A GB3401872 A GB 3401872A GB 3401872 A GB3401872 A GB 3401872A GB 1367225 A GB1367225 A GB 1367225A
Authority
GB
United Kingdom
Prior art keywords
active region
layer
wafer
substrate
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3401872A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB3401872A priority Critical patent/GB1367225A/en
Publication of GB1367225A publication Critical patent/GB1367225A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

1367225 Semi-conductor devices STANDARD TELEPHONES & CABLES Ltd 20 July 1972 34018/72 Heading H1K A semi-conductor device wafer having an active region formed on a substrate has its substrate surface bonded to a metal block and the whole of the active region surface is provided with a metal layer overhanging the edges of the wafer. As shown, a Gunn diode comprises an active region 2 of N-type GaAs epitaxially deposited on a thinned N<SP>+</SP>-type GaAs substrate 3. The major faces are provided with Sn-Ag contacts, 4, 5 and the substrate contact is soldered to a Cu heat sink block 8. The active region contact is provided with a layer 6 of Au, Ag or Cu by electroplating material over the whole of the active region contact of a wafer, and masking and etching to divide the wafer into a plurality of bodies 1 with overhanging layer 6. In pulsed operation the heat generated in the device during the on periods flows to the heat sink 8 and the plated layer 6 and during the off periods the heat stored in layer 6 flows back through the device to the main heat sink 8.
GB3401872A 1972-07-20 1972-07-20 Semiconductor device mounting arrangement Expired GB1367225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB3401872A GB1367225A (en) 1972-07-20 1972-07-20 Semiconductor device mounting arrangement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3401872A GB1367225A (en) 1972-07-20 1972-07-20 Semiconductor device mounting arrangement

Publications (1)

Publication Number Publication Date
GB1367225A true GB1367225A (en) 1974-09-18

Family

ID=10360354

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3401872A Expired GB1367225A (en) 1972-07-20 1972-07-20 Semiconductor device mounting arrangement

Country Status (1)

Country Link
GB (1) GB1367225A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2412168A1 (en) * 1977-12-15 1979-07-13 Silicium Semiconducteur Ssc OVERVOLTAGE DIODES

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2412168A1 (en) * 1977-12-15 1979-07-13 Silicium Semiconducteur Ssc OVERVOLTAGE DIODES

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Legal Events

Date Code Title Description
PS Patent sealed
435 Patent endorsed 'licences of right' on the date specified (sect. 35/1949)
PCNP Patent ceased through non-payment of renewal fee