GB1366231A - Method of maufacturing a four zone semiconductor device - Google Patents
Method of maufacturing a four zone semiconductor deviceInfo
- Publication number
- GB1366231A GB1366231A GB1686973A GB1686973A GB1366231A GB 1366231 A GB1366231 A GB 1366231A GB 1686973 A GB1686973 A GB 1686973A GB 1686973 A GB1686973 A GB 1686973A GB 1366231 A GB1366231 A GB 1366231A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- layer
- cathode
- anode
- insulant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 239000012535 impurity Substances 0.000 abstract 6
- 239000002019 doping agent Substances 0.000 abstract 2
- 239000011521 glass Substances 0.000 abstract 2
- 229910014299 N-Si Inorganic materials 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- UFULAYFCSOUIOV-UHFFFAOYSA-N cysteamine Chemical compound NCCS UFULAYFCSOUIOV-UHFFFAOYSA-N 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 230000004048 modification Effects 0.000 abstract 1
- 238000012986 modification Methods 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 229910052596 spinel Inorganic materials 0.000 abstract 1
- 239000011029 spinel Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0817—Thyristors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7436—Lateral thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
Abstract
1366231 Semi-conductor devices NATIONAL CASH REGISTER CO 9 April 1973 [20 April 1972] 16869/73 Heading H1K A 4 zone semi-conductor device, e.g. a MOST with 1st and 3rd zones of one conductivity and 2nd and 4th zones of a second conductivity is connected at 12 in a circuit 10 (Fig. 1) with a P-type anode and cathode base 14, 18 and a N- type anode base and cathode 16, 20. An insulated gate 22 spans cathode base 18 with electrode 26 of, e.g. Al overlying insulant 24. Battery 30 energizes anode 14 and cathode 20 over load resistor 22 and switch 36, while battery 30 energizes gate electrode over switch 44 by which it is alternatively grounded. In operation (Fig. 2) curve A represents conducting state and curve B nonconducting state, with a holding current at point E. Initially the gate electrode is grounded and the device is de-energized to be nonconducting. Closure of switch 36 develops a voltage/current characteristic B with operation at point D, the intersection of load line CD. Closure of switch 34 causes the device to assume its conductive characteristic A with operating point C. Restoration of switch 34 holds the device conducting until anode current is reduced below the holding value E, when the device resumes its nonconducting state. In fabrication an insulant, e.g. spinel support has grown thereon a semi-conductor crystal 42 of, e.g. high resistivity N-Si on which an insulant layer 44 of, e.g. SiO 2 is deposited or thermally grown, in which cathode and anode openings 46, 48 are etched. A layer 50 of a glass containing distributed P and N impurities, e.g. As and Bo is then, e.g. sputtered on and removed except in the region of the cathode opening and is overlain by a further layer of glass 52 containing only P-type impurities, e.g. Bo (Fig. 3c). The device is heated for thermal diffusion of the impurities into layer 42 so that P-regions 54, 58, 62 and N-regions 56, 60 exist therein; the P- impurities penetrating more deeply than the N- impurities. Regions 54, 58 are interconnected (not shown), and region 56 has a high concentration and low resistivity as cathode, region 58 has medium concentration and medium resistivity as cathode base, region 60 has high resistivity as anode, base and region 62 has high concentration and low resistivity as anode. The layer 44 is etched away to an appropriate depth (or directly to region 58 with subsequent regrowth) and conductive material, e.g. Al is deposited at 68, 70, 72 in openings 46, 64, 48 to contact region 50, insulant layer 66, and region 62, and may be connected to other points of an integrated circuit. (Fig. 3e.) In a modification, a N-type Si layer of high resistivity is grown epitaxially on a P-type Si substrate, an insulant layer is grown thereon, and P-type regions are diffused through openings into the N-type layer. Anode and cathode openings are etched in the insulant layer and a PN dopant source is applied as described and removed save for that in the anodic opening. A further P dopant source is deposited as described and the impurities are in-diffused to part depth of the epitaxial layer to leave a N-region in a P-region, and a P-region distinct therefrom, to form the required 4 zone device. A gate electrode is deposited in an opening of the insulant layer to span the first P-region, and metal layers are deposited in the openings to form a gate. (Figs. 4a to 4e, not shown.)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US24605972A | 1972-04-20 | 1972-04-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1366231A true GB1366231A (en) | 1974-09-11 |
Family
ID=22929171
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1686973A Expired GB1366231A (en) | 1972-04-20 | 1973-04-09 | Method of maufacturing a four zone semiconductor device |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS4918581A (en) |
CA (1) | CA975088A (en) |
DE (1) | DE2319644A1 (en) |
FR (1) | FR2181052B1 (en) |
GB (1) | GB1366231A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5128762A (en) * | 1974-09-04 | 1976-03-11 | Tokyo Shibaura Electric Co | TATEGATASETSUGODENKAIKOKAHANDOTAISOCHI NO SEIZOHOHO |
FR2488046A1 (en) * | 1980-07-31 | 1982-02-05 | Silicium Semiconducteur Ssc | DMOS controlled semiconductor power device - uses DMOS FET to drive thyristor with photodiodes deposited on insulating layer with power device using most of substrate area |
US4595941A (en) * | 1980-12-03 | 1986-06-17 | Rca Corporation | Protection circuit for integrated circuit devices |
-
1973
- 1973-04-06 CA CA168,090A patent/CA975088A/en not_active Expired
- 1973-04-09 GB GB1686973A patent/GB1366231A/en not_active Expired
- 1973-04-18 DE DE19732319644 patent/DE2319644A1/en active Pending
- 1973-04-20 JP JP4427073A patent/JPS4918581A/ja active Pending
- 1973-04-20 FR FR7314512A patent/FR2181052B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2181052B1 (en) | 1978-05-12 |
FR2181052A1 (en) | 1973-11-30 |
CA975088A (en) | 1975-09-23 |
DE2319644A1 (en) | 1973-10-25 |
JPS4918581A (en) | 1974-02-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |