GB1336296A - Integrated circuit arrangments - Google Patents

Abstract

1336296 Integrated circuits ARBEITSSTELLE FUR MOLEKULARELEKTRONTK 2 Dec 1970 57268/70 Heading H3T [Also in Division G1] An integrated circuit with hot redundancy consists of a plurality of identical subsystems 3, 4 driven by a common signal source 1 or 2 and having their outputs connected in parallel and individual means 5, 6, Figs. 1 and 2, 10, 11, Figs. 3 and 4 for determining whether each subsystem is non-defective or defective is connected to the outputs of the subsystems. The means 5, 6; 10, 11 includes a common summation device 7. By hot redundancy is meant that all the subsystems are initially electrically interconnected during manufacture without any individual functional testing. The circuit of Fig. 1 includes differentiators 5 and 6 and the output of the summation device is fed to a memory 8. The circuit details of Fig. 1 are shown in Fig. 2. Fig. 3 includes switches 12 and 13 and switch control devices 10, 11 which are shown in detail in Fig. 4 and each include memories 15 and 17 and a discriminator 16. After the circuit of Fig. 3 is switched on and tested, a 0 signal or a 1 signal must occur during the operating time at output 18 depending on whether the subsystem 3 is defective or non- defective. The outputs of the memories 15 and 17 are a predetermined signal 0, when the circuit is switched on. The predetermined output of the subsystem 3 considered is fixed in the memory 15 and is compared with the signal at the output of the subsystem after the input signal has been changed. If the input signals of the discriminator 16 are the same corresponding to the associated subsystem being defective a 0 signal output occurs at 18 and switch 12 is open. If the input signals of the discriminator 16 are different corresponding to the associated subsystem being non-defective a 1 signal output occurs at 18 and switch 12 is closed. A pulse supplied to an input 19 ensures change over of the subsystems 3 and 4 if non- defective after a decay of the pulse from capacitor 21. Details of the Fig. 3 circuit are disclosed in Fig. 5 (not shown).