US3286234A - Satellite commutator having reed relay matrix - Google Patents

Description

A. F. HOGREFE A 3,286,234

SATELLITE COMMUTATOR HAVING REED RELAY MATRIX I5 Sheets-Sheet 1 Filed May '7, 1963 ATTORNEY Nov. 15, 1966 A. F. HOGREFE 3,286,234

SATELLITE COMMUTATOR HAVING REED RELAY MATRIX 5 Sheets-Sheet 2 Filed May 7, 1963 RESET www ATTORNEY Nov. 15, 1966 A. F. HOGREFE 3,286,234

SATELLITE COMMUTATOR HAVING REED RELAY MATRIX Filed May 7, 1963 5 Sheets-Sheet 5 FROM GATE DRlvE AMPLIFlER RESET i I /04 Y @e /02l g 88. 55' g i l f Pla: '84,@5i l 36 5" 56' hl I /03 jI 56 90' C?? i I 96' l l 52 n l 94, F/ G 3 54' 37 66\ SE 70' /0\0 msg -//0 65\ k $721 6a 35, 57 l :To 65 /20 To MoNnomNe clRculT /20 To MoN|ToR|NG clRculT OUTPUT ARTHUR F. HOGREFE INVENTOR.

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ATTORNEY United States Patent 3,286,234 SATELLITE COMMUTATOR HAVING REED RELAY MATRIX Arthur F. Hogrefe, Silver Spring, Md., assignor to the United States of America as represented by the Secretary of the Navy Filed May 7,1963, Ser. No. 278,793

8Claims. (Cl. 340-166) This invention relates in general to time multiplexing equipment and, more particularly, toan electro-mechanical commutator utilizing reed relays in its connection matrix. v

The present invention generally -rese-mbles commutating equipment which is `well-known and has existed for many years. However, the instant invention includes several additional unique features which render it singularly suitable for application in satellite systems. More specifically, it employs reed relays for making successive connections, and controls the operation of these relays by reliable electronic circuits, thereby combining the advantages of both electronic circuits and mechanical devices. v

The instrumentration of the electronic circuits of the present invention incl-udes safety features for eliminating any interaction between satellite monitoring systems, in the event of any catastrophic.malfunction during launch affecting theinterconnection of -any twoor more channels of the commutator. Additionally, theinstant invention is designe-d to operate on a 75% duty cycle, thereby reducing power drain and, more importantly, facilitating the design of ground equipment which is used in conjunction thereto.

Another beneficial feature resulting from the employment of electronic control .circuitry is the use of a series of connected flip-flops as counters, which flip-flops have one of their stages connected to a common inhibiting current source.V This current source acts .as a safety feature whereby only one flip-flop can be energized at a time in contradistinction to the use of a voltage level, which level allows the energizing of more than one stage under noisy operating conditions. Such .a spurious operation persists indefinitely until reset by turn off of the ring counter, and causes the loss of information during that period. Also, the iiip-flop ring counters of the present invention have bias networks to prevent la complete circuit failure upon a momentary loss o-f the single existing excited flipiiop due to noise. These networks automatically cause the first stage of each of the counters to be turned on and allow normal operation to begin again.

The mechanical advantages lent to the instant invention through the use of reed relays include complete isolation between the .separate satellite systems which are gathering information, and a resulting absence of cross talk between channels. Therefore, a commutator can be made with any number of channels without any inherent limit. Additionally, the use of the reed relays permits the sensing of signals 100 t-o 100() times smaller than is possible with the use of an electronic connecting matrix.

One object of the present invention, therefore, resides in the provision of a satellite commutator which is suited for yremote operating conditions by the use of built-in safety features.

Another object of the invention is to provide a satellite commutator which exhibits zero cross talk and provides suicient isolation between input channels.

A further object of the invention is toprovide a satellite commutator which is able to resolve very small input signals.

A still lfurther object of the invention is to provide a satellite commutator which allows the employment of hi-gh accuracy ground equipment.

and drive' circuit.

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yOther objects yand many of the attendant advantages of this invention will be readily appreciated as the same becomes better understoodV by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a generalized block diagram of the instant invention;

FIG. 2v is a schematic diagram of the current source, bias network Aand first counter stage -of the X-axis driver shown in FIG. l;

n FIG. 3 is a schematic diagram of the current source, bias network, first counter stage and positive amplifier employed in the Y-axis driver;

FIG. 4 is -a schematic `diagram of the reed relay matrix employed in the instant invention showing ho-w an individual relay is energized; `and FIG. 5 shows typical relay circuits employed in the instant invention.

Briefly, the instant invention comprises a reed relay matrix for connecting the output of various electronic circuits dispersed within the satellite, which circuits monitor the functioning of the satellite at selected points. The connecting matrix is driven Iby aplair of counters which sequentially energize the relays in the matrix, which counters in turn are synchronized and driven by a clock In operation,v the clock and drive circuit may either free run or be synchronized to an external source of extreme timing accuracy. However, the embodiment shown is free running.

Referring to FIG. l, the clock and drive circuit 1,

employed in the instant invention has three output signalls, the first of which is connected to an X-axis driver 2, which driver includes a plurality of counters 3, the second is connected to a Y-axis driver 4, which driver includes a plurality of counters 5, and the third is connected to a plurality of positive amplifiers 7. The counters 3 are consecutively connected together and form a one to six counter, while the counters 5 are conne'cted together and form a one to five counter. The outputs of the counters 3 directly drive the X-axis of a reed relay matrix 9, while the outputs of the counters 5 are first connected to the amplifiers 7 for the proper polarity inversion before being applied to the Y-axis of the matrix. Only one of the lines from each of the counters 3 and 5 is energized at any time. A relay positioned in the matrix 9 and located at the intersection of the pair of energized lines is activated, thereby connecting one output of ya satellite monitoring circuit to the satellite transmitting'equipment rfor transmission to the ground.

For clarity in the relay matrix 9, shown schematically i in FIG. l and in greater detail in FIG. 4, the lines drawn horizontally willl be designated rows, whereas those arranged vertically will be called columns The clock and drive circuit 1 contains features whereby it may either be free running or synchronized to an external source. A pair of cascaded amplifiers 14 and 16 take un external repetitive synchronizing signal when applied *o an input terminal 17 and apply it t-o an astable dip-flop 1'8, which flip-flop would also free run in the absence of the input synchronizing signal. The fiip-flop 18 has two output signals, one of which is applied to a divide by 2 tiip-fiop 20, and the other is applied to a gated amplifier circuit 22. The flip-flop 20` produces an output signal at a rate one-'half its input signal, which output signal is also applied to the gated amplifier 22. The two input signals applied to the input of the amplifier 22 are combined at its input in the form of a logical or gate operation so that the output signal has a duty factor of The output from the amplifier 22 is applied to a drive amplifier 24, which amplifier increases the power of its input signal and applies its output signal to a one-shot Hip-flop 26 and a gate drive amplilier 28. The one-shot flip-flop 26 develops the drivepulses for advancing both the counters 3 and 5, while the drive amplifier 28 produces the gating signal applied to the positive going amplitiers 7 and produces the 75% duty factor for-the reed connecting matrix 9. The ip-flop 26 is connected to a current source 29 employed in both the X-axis and Y- axis drivers 2 and 4, which drivers additionally employ bias networks 30 connnected to voltage source terminals 31 and to the rst counter stages of each of the drivers.

One of the currentsources 29 for the counters 3 is shown schematically in FIG. 2, and includes a pair of transistors 32 and 33.v A base lead 34 of the transistor 32 is connected to ground 35 by a series connected resistor 36 and diode 37, which diode 37 is connected so as to maintain a slightly positive signal at its junction with the resistor 36. Additionally, the base lead 34 of the transistor 42 is connected to the source of positive potential 31 by a series connected diode 38 and resistor 39, which source 31 may be a positive 22 volts, and which diode 38 is connected s o as to allow a ilow of biasingl current from the source 31 to ground 35 through the divider 39, 38, 36 and 37. A capacitor 40 is connected in parallel with the series connected diode 38 and resistor 39. An emitter lead 41 of the transistor 32` is connected to the base lead 42 of the transistor 33 and aA collector lead' 43 of a transistor 3 2`is connected to a collector lead 44` of the transistor 33. The emitter lead 41 of the transistor 32 is connected to the 'potential source 31 by a resistor 45, and an emitter lead 46 of the transistor 33 is connected to the potential source 31 by a pair of parallel connected resistors 48 and 49. The values of the resistors 48 and 49 are chosen to obtain a 16 volt level at' the emitter lead'46 of the transistor 33 when one ip-op only is conducting.

The biasingnetwork of the rst counter 3 is used to reset the first counter Whenever the one on stage of the X-'axis driver' is lost, and comprises a pair of resistors 50 and 51,' a capacitor S2, and ,a diode 53. The

resistors 50 and 51 are connected in series with an addi-iA tional resistor 54 between the potential source 31 and ground 35. The capacitor 52 is connected from lthe junction of the resistors 50 and 51 to ground `35, and the diode 53 connects a base lead 55 of a transistor 56 to the junction of the resistors 50 and 51, and functions to pass negative signals to said base of the transistor 56.

The remaining circuitry for the rst ip-iiop counter stage is identicalfor the additional ve counter stages, which stages include, in addition to the transistor 56, a' v second transistor 57, which transistor,"` has a diode 58 the matrix 9 by means of identical lines 62. An emitter lead 65 of the transistor 57 is connected to the junction of the resistor 36'and the diode 37 by a line 66, -and is also connected to the emitter lead of the corresponding transistor in the next counter Istage by a line 68. A base lead 70 of the transistor 57 is connected to ground 35 by a resistor 72, and to a collector lead 76 of the transistor 56 byY a resistor 74. The input signal from the one-shot flip-flop 26 is applied to the collector lead 44 of the transistor 33 by a line 78, and said collector lead 44 is connected to an emitter lead 79 of the transistor 56 by a line 81 and to each succeeding emitter leads of corresponding transistors in the following counter stages by a line 82. A series connected diode 83 and to the base lead 55.

capacitor 84, a line 85 and a diode 86 connect the collector lead 76 of the transistor'56 to a base'lead 55 of the corresponding transistor, in the following counter stage 3, and constitute the circuit over which trigger pulses pass to energize the subsequent counter ip-flop stage. The `diode 83 is connected to pass positive going signals from the collector lead 76 to the base lead 55 and the diode 86 is connected to pass negative signals A line 87 is connected between the junction of the diode 83 and the capacitor 84, and the junction of the resistors 51 and 54.

A second biasing yarrangement for the iirst counter stage is the standard biasing arrangement for the remaining stages -in'the X-axis driver and comprises, in addition to the diode 86, -a pair of resistors 88 and 90 and an additional diode 94. The resistor 88 is connected between the potential source 31, and the base Ilead 55 of the transistor 56. The diode 86" is connected in series with the resistor 90` and the diode 94 between the base lead 55 of the transistor 56 and the collector lead `60 of the transistor 57. Both diodes are 4arranged to pass negative sig` nals from the collector leai 60 to the base lead 55. A resistor 96 is connected between the junction of the resistor 90 rand the diode 94, and the junction of the capacitor continuous recycling.v 'l

' FIGL 3 shows the positive amplifiers employed in the Y-axis driver, including considerable circuitry that is identical with that described in FIG. 2. Therefore the gsame numbers raised to the prime are used to identify components identical to tho-se used in FIG. 2. The col-y a transistor `104. An emitter lead 105 of the transistor 104 is connected to the gate drive amplifier 28 by a series connected diode 106 and a line 107, and the collector lead 108 o-f the transistor 104 is connect-ed to ground 35 by a resistor 109 and to the rst row of the reed relay matrix 9 by :a line 110; Succeeding positive amplifiers tion. Each column of t-he matrix is energized by a separate line 62 or 62V from one of the counter stages 3 contained -in the X-axis driver 2, and each row is ener- Igized by a separate l- ine 110 or 110 from one of the counter stages 5 contained in the Y-axis driver 4. Since the drivers 2 and 4 each employ a mutually prime number ot counters, which numbers have no common factor other than one, the relays are energized in ythe order indicated in FIG. 4 by consecutive K numbers K1 through K30.

A typical re'lay energizing circuit 114, shown in FIG. 4, comprises a diode 115 in series with an individual relay coil 17, which elements 115 and 117 are connected between `the lines k1105and 62, and a .diode 119 connected across the relay Icoil 117 to provide damping. However, sometimes a icapacitor is substituted for the diode 119 to allow an oscillatory `damping and to prevent sticking of the matrix 9 by lines the re1=ay contact arm 120 closes, the signal from one of the monitoring circuits is transferred to t-he output terlm'inal 123 for transmission over lthe satellite transmission system. The resistors 121 and 122 reduce the signal amplitude for proper signal transfer within the system range. The value-s of these resistors 121 and 122 depend upon the type of monitori-ng circuit to which it is connected but are easily determined yaccording to well-known design principles; however, the resistor 121 shoul-d be larger than 1000 ohms to prevent interaction of separate satellite monitoring systems, which interaction occurs Iupon the simultaneous unintentional closure of two or more relay a-rmfs 120.

In operation, tihe free running flip-flop of the clock and drive circuit 1 develops a series of pulses for use as the basic source of timing pulses thro-ughout the commutator. A-n additional logical or gating circuit 22 develops a drive waveform of about two seconds period with a 75% symmetry, that is, `a wave-form which is at 'ground potential 25% 'of the time and at a positive voltage potential t'h'e remaining 75 of the time. This output waveform simultaneously drives both the X-axis and the Y- axis drivers 2 and 4. Since the first counter stage 3 and 5 of each axis driver is biased in such a manner as to assume the on condition in the absence of any input signals, both counters will advance sequentially from the first counter stage to the last stage, which stage then resets t-he first stage yto continue recycling. A typical counter stage 3 .and 5 utilized in both .the X-axis and Y- axis drivers 2 and 4 consists of the pair of transistors 56 and `57, as best seen in FIG. 2. ' Ilhe transistors 56 and 57 are referenced from a voltage that is derived vfrom the current source 29, which source wiil sustain stable circuit conditions if, and -only if, a single counter stage is in the on condition. These counter stages are complementary, that is, both transistors are on at the same time. If the second counter stage shown in FIG. l, is off and `the first counter stage shown schematically in FIG. 2 is o-n, the following conditions are present: the capacitor 84 has a 15 vo'lt bias on the lead connected to the `diode 83 and -a 20 volt bias on the lead connected to the diode 86. Thus, there is a potential of about five volts across this capacitor and if the rst counter stage is turned ofi the rinput side is pulled toward ground by the resistor 54 and a resulting bias of 7 to 8 volts is applied to the 'base lead 55 of the transistor S6', due to the divide-r action of the resistors 88 and 54. Such a voltage change occurs during the period when the output drive waveform from the one-shot multivibrator 26 clamps the collectors 43 :and 44 of the transistors 32 and 33 to ground. The capacitor 84 begins to charge and the bias is sustained at the base lead 55 of the transistor 56',

wihichV bias causes the transistor 56 to turn on when the positive period of the input waveform `from the one-shot multivibrator 26 releases the current source, by enabling the second counter -stage t-o regenerate into the on state. The bases of the remaining transistors 55' are biased at 22 volts under the :same condition and have no tendency to turn on while the 'base lead 55 -of the transistor 56 is bia-sed at 17 volts, a significantly greater potential than that allowed t-o turn the transistor 56 back on again.

The first counter stage is always turned on if all the other counter stages are 'off, due to the special D.C. 'bias arrangement found only in the first counter stage, which arrangement consist-s of the pair of resistors 50 and 51, the capacitor S2 andthe diode 53. The positive turn on of the first counter stage occurs when the remaining stages are 'off, which condition allows the current source line 81 to rise almost to :the supply voltage, therefore placing 22 volts .at the emitter 79 -of the transistor 56.` Since the special bias arrangement places 18 volts on the 'base llead 55 `of the transistor 56, itis biased on..

The transistor 57 provides the regenerative action necessary to place tlhe transistor '56 into full conduction, while the diode clamp 58, which is connected to the potentia'l source 31, is provided to protect the collector 60 of the ltransistor 57 in the event of improper commutator operation and large ki-ck voltage from the relay coils. The diode 86' is used in the base lead 55 of the transistor 56 t-o prevent the turn on of the previous stage from placing excessive voltage across the inter-nal base to collector junction of the transistor 56. The diode 83 prevents the voltage across the coupling capacitor 84 from feeding back Iinto the base of the transistor 57 after it is turned off The operation of the Y-axis driver 4 is identical to that of the X-axi's driver 2 just described. However, each stage drives into a positive amplifier 7, as seen in FIG. 3, by .the series connected line 100 and t-he resistor 101. The positive amplifier 7 Iobtains the negative voltage from the colll-ector llead 60 of the transistor 57 and inverts it to a positive voltage signal Ihaving a magnitude of approXimately the volt-age source at the connection of the line 110 with the resistor 109.

Therefore, a positive signal from the Iline 110 in FIG. 3 and a negative signal from the line 61 in FIG. 2 are applied across the relay coil 117, as seen in FIG. 4, to energize the relay.

The instant invention is stable in operation, having a minimum of change in its timing waveforms. This stability, in addition to purposely grounding two or three consecutive channels, allows positive frame synchronizing with supporting ground equipment.

Component values which have been selected for use in a preferred embodiment of the instant invention are as follows:

R36 ohms 121K R39 do 38.3K R45 do 17.8K R50, R72, R74, R do 31.6K R51 do 68.1K R54 do 8.25K R74, R101 do 14.7K R88 do 46.4K R96 do 422K R102 d0 10K R109 do 56.2K C40, C52 /rf .01K C84 af .02K D37, D53, D58, D83, D86, D94, D106 IN 3070 D38 IN 3064 Q32, Q56 320S2 Q33, Q104 2N2303 Q57 2N1711 Obviously, many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may De practiced otherwise than as specifically described.

What is claimed is:

1. An electromechanical commutator circuit, prising,

a first flip-dop for developing basic timing signals,

a second flip-flop driven by said first flip-flop for dividing in half the frequency of the basic timing signals,

a gating amplifier connected to the output of both of said flip-flops for performing a logical or function in generating a waveform having a partial duty cycle,

a one-shot flip-flop electrically connected to said gating amplifier for developing drive pulses,

a drive amplifier electrically connected to said gating amplifier for furnishing gating pulses,

an X-axis driver actuated by said one-shot flip-flop for sequentially developing a plurality of energizing voltages,

a Y-axis driver actuated by said one-shot dip-flop and controlled by said drive amplifier for sequentially developing a second plurality of energizing voltages, and

COIII- a plurality of reed relays formed as a matrix and connected to said X-axis driver and to said Y-axis driver, whereby said pair of energizing voltages is consecutively applied to each of said relays for activation thereof.

2. A commutator circuit as recited in claim 1, wherein said X-axis driver comprises,

a plurality of flip-flops connected to form a recirculating counter,

a current source connected to each of said fiip-flops for individually furnishing an energizing voltage to each of said flip-flops,

means for initially biasing the first of said flip-fiops to conduction, and

means connected between consecutive flip-flop stages for sequentially energizing the remaining plurality of fiipflops.

3. A commutator circuit as recited in claim 1, wherein said Y-axis driver comprises,

4. An electromechanical commutator circuit, compris` lng,

a first flip-Hop for developing basic timing signals, a second flip-flop driven by said first flip-flop for dividing in half the frequency of the basic timing signals, a gating amplifier connected to the output of both of said fiip-fiops for performing a logical or function by generating a waveform having a 75% duty cycle, one-shot flip-flop electrically connected to said gating amplifier for developing drive pulses,

a drive amplifier electrically Aconnectedto said gating amplifier for furnishing gating pulses,

a first plurality of flip-flops connected to form a first recirculating counter for generating an energizing voltage,

a second plurality of fiipffiops connected to form a second recirculating counter,

currentsources operated by said owne-shot-fiip-op and connected to each of said pluralityrof fiip-fiops for individually furnishing an energizing voltage to each of said flip-flops, means for initially biasing the first of said flip-fiops in said first and said second counters to conduction, means connected between consecutive fiip-flop stages in said first and said second counters for sequentially energizing the remaining pluralityl of flip-flops in each of said counters,

a positive amplifier connected to each of said flip-flops' in said second counter and controlled by said drive amplifier for generating a second energizing voltage, and

a plurality of reed relays formed as a matriX and connected to said first counter and to said positive arnplifiers, whereby each of said relays is consecutively activated by said pair of energizing voltages.

5. A commutator circuit as recited in claim 4, wherein said current source comprises,

a rst transistor having a base, an emitter and a collector,

the collector of said first transistor being electrically connected to said one-shot fiip-flop and to each of said fiip-fiops in its respective counter,

l a second transistor having an emitter, a base and a collector, the collector of said second transistor being connected to the collector of said first transistor, means for biasing said first transistor to conduction in the presence of a positive potential signal from saidV one-shot flip-flop, the emitter of said first transistor being connected to the base of said second transistor for causing said second transistor to conduct at the same time the first transistor conducts, and means connected to the emitter of both of said transistors for regulating the flow of current through said transistors, whereby a stable current level is set at the emitters of said transistors, which level is capable of causing only one of the counter stages to be placed in conduction. 6. A commutator circuit as recited in claim 4, wherein one of said counter flip-flops comprises,

a first PNP transistor having a base, an emitter and a collector,

the emitter of said first transistor being connected to connected to the base of said second transistor and to ground,

the emitter of said second transistor being connected to a first positive potential,

means for connecting the collector of said second transistor to a second positive voltage potential greater than said first positive potential,

means for connecting the collector of said second transistor to the base of said first transistor and to the second source of positive potential, and

means for biasing said first transistor to conduction upon operation of said sequential energizing means in transferring a triggering pulse from the first transistor of a prior counter flip-flop.

7. A commutator circuit as recited in claim 4, wherein said sequential energizing means comprises,

a capacitor electrically connected to said collector of said first transistor for charging during the period of conduction of the first counter flip-fiop and for discharging during the grounding of said current source to create a trigger pulse for application to said base of said subsequent counter Hip-flop,

a first diode electrically interposed between said capacitor and the collector of said first transistor on said first counter flip-Hop for preventing the voltage across said capacitor from feeding back into the collector of the first transistor and that had just been on, and

a second diode interposed between said capacitor and the base of the first transistor of said subsequent counter flip-fiop for preventing the turn on of said first counter flip-flop from placing excessive voltage across the base to collector junction of said subsequent counter flip-flop.

8. A commutator circuit as recited in claim 6, wherein said collector connecting means of said second transistor further includes, v

a diode clamp electrically interposed between the collector of said second transistor and said second potential source for protecting said second transistor from large voltage surges caused by improper commutator operation.

No references cited.

NEIL C. READ, Primary Examiner.

H. PITTS, Assistant Examiner.

Claims (1)

1. AN ELECTROMECHANICAL COMMUTATOR CIRCUIT, COMPRISING, A FIRST FLIP-FLOP FOR DEVELOPING BASIC TIMING SIGNALS A SECOND FLIP-FLOP DRIVEN BY SAID FIRST FLIP-FLOP FOR DIVIDING IN HALF THE FREQUENCY OF THE BASIC TIMING SIGNALS, A GATING AMPLIFIER CONNECTED TO THE OUTPUT OF BOTH OF SAID FLIP-FLOPS FOR PERFORMING A LOGICAL "OR" FUNCTION IN GENERATING A WAVEFORM HAVING A PARTIAL DUTY CYCLE, A ONE-SHOT FLIP-FLOP ELECTRICALLY CONNECTED TO SAID GATING AMPLIFIER FOR DEVELOPING DRIVE PULSES, A DRIVE AMPLIFIER ELECTRICALLY CONNECTED TO SAID GATING AMPLIFIER FOR FURNISHING GATING PULSES, AN X-AXIS DRIVER ACTUATED BY SAID ONE-SHOT FLIP-FLOP FOR SEQUENTIALLY DEVELOPING A PLURALITY OF ENERGIZING VOLTAGES, A Y-AXIS DRIVER ACTUATED BY SAID ONE-SHOT FLIP-FLOP AND CONTROLLED BY SAID DRIVE AMPLIFIER FOR SEQUENTIALLY DEVELOPING A SECOND PLURALITY OF ENERGIZING VOLTAGES, AND A PLURALITY OF REEDS RELAYS FORMED AS A MATRIX AND CON-

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