SU532830A1 - Control device of integrated circuits - Google Patents

Description

one

The invention relates to computing hardware and can be used in automated systems for controlling integrated circuits (ICs) with dynamic logic.

The devices of the control ICs, containing a pulse generator, a cipher counter, a block of matching elements, are known. However, such devices do not provide control of ICs with combined outputs in dynamic mode, which in one of the power cycles are the input to the other cycle - outputs.

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A system of automatic control of large integrated circuits is also known, which contains a control unit, a memory unit, an amplitude discriminator connected to the OR element 2j.

However, well-known devices for controlling integrated circuits do not provide fast re-switching of the combined IC outputs from the low-resistance outputs of the memory unit to the high-impedance inputs of the amplitude discriminators and do not allow

the role of such ICs with a frequency exceeding the frequency of accessing the memory unit.

The purpose of the invention is to expand the functionality of the device.

This is achieved by the fact that two pairs of keys of input circuits and expected output tests, which are connected by information inputs to the outputs of the block, are entered into the integrated circuit control device containing the control unit, the memory unit and the amplitude discriminator connected to the OR element, and inputs to the outputs of the control unit, and the outputs of the keys of the input circuits are connected to the control unit's modes (IC and information input the amplitude discriminator, the comparison input of which is connected to the outputs of the keys of the expected output tests, and the enable input of the amplitude discriminator is connected to the input of the control unit.

Claims (2)

Such a device makes it possible to control integrated circuits with combined outputs with a frequency exceeding the frequency of accessing the memory block as a result of fast re-switching of the object's leads from the low-resistance outputs of the memory block to the high-resistance inputs of amplitude discriminators. The drawing shows a structural electrical circuit of an IC control device for one output of a control object. The terminals of the control object 1 are connected to the dielectric input of the amplitude discriminator 2 and through transistor switches 3 and 4 of the input circuits to the outputs of different bits of the storage unit 5 for storing test combinations. The control inputs of the transistor switches 3 and 4 are connected to the corresponding outputs of the control unit. 6, the corresponding outputs of which are connected to the control inputs of the transistor switches 7 and 8 of the expected output tests to the enable input of the amplitude drive of the riminator 2. The keys 7 and 8 are connected between the corresponding the outputs of the memory block and the input of the amplitude discriminator. The output of the amplitude discriminator 2 is connected to the input of the element OR 9 The input influences allocated by memory 5 are fed to the pegs of the control object 1 only at the times determined by pulses arriving at the control inputs of transistor switches 3 and 4 from the output of control unit 6 generating strobe pulses. Moreover, the frequency of changing the input information arriving at the corresponding terminal of the control object may exceed the maximum frequency of information output by the memory unit 5. During one cycle of information output by the memory block 5, the input information is double-changed at the control object terminal. The input information supplied to the terminal of the control object 1 simultaneously arrives at the input of the amplitude discriminator 2. However, the amplitude discriminator does not trigger because the control unit 6 does not issue a permit pulse (output gating) to the amplitude discriminator 2. A strobe pulse to the amplitude discriminator 2 is applied in time, when the output signal appears on the terminal of the control object 1. The transistor switches 3 and 4 are closed at the same time, and the output signal is not shunted by the low-resistance outputs of memory unit 5. The output signal from the control object terminal 1 is fed to the input of the discriminator 2 simultaneously with the enabling pulse of the control unit 6, the input and fflylc to the amplitude discriminator 2. At the same time, the control unit 6 opens one of the transistor kg-capacitors 7, 8 of the expected input tests, which allow the passage of information from the output of the memory unit, which must correspond to the output signals of the control object at a given time with a properly working control object 1 (the expected test combinations). The amplitude discriminator 2 captures the amplitude of the output signal of the control object, compares it with the expected information provided by memory 5 through the keys 7, 8, and if the signals do not match, it generates an error signal at the input of the OR element, the output of which about the presence of marriage. Claims of the Invention Control Unit integrated circuit 1X circuits comprising a control unit, a memory unit and an amplitude discriminator connected to the OR element, with the fact that, with the functionality extension chain, two pairs of input circuit keys and expected output keys are entered into it gestas, which are connected by information inputs to the outputs of the memory unit, and the control inputs are connected to the outputs of the control unit, and the outputs of the keys of the input circuits are connected to the terminals of the control object and the information inputs of the amplitude dis riminatora, comparing the input of which is connected to the outputs of the key expected vyhoschvyh tests, and the resolving input amplitude discriminator soe- of the connections with the output control block. A l 7 II J 8 H h h h