GB1327713A - Integrated circuits - Google Patents

Integrated circuits

Info

Publication number
GB1327713A
GB1327713A GB4889671A GB4889671A GB1327713A GB 1327713 A GB1327713 A GB 1327713A GB 4889671 A GB4889671 A GB 4889671A GB 4889671 A GB4889671 A GB 4889671A GB 1327713 A GB1327713 A GB 1327713A
Authority
GB
United Kingdom
Prior art keywords
channel
polycrystalline
zone
dopant
channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4889671A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1327713A publication Critical patent/GB1327713A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

1327713 Semi-conductor devices SIEMENS AG 21 Oct 1971 [27 Oct 1970] 48896/71 Heading H1K An interconnection between elements in an integrated circuit is provided at least in part by a buried zone A 2 of the monocrystalline semiconductor body and a polycrystalline channel 9 connecting the zone A 2 to the surface of the body, the zone A 2 and channel 9 being of the same conductivity type. The surface-emergent area of the channel 9 may be connected directly to a zone of one of the circuit elements, or may be indirectly connected thereto via a conducting track overlying an insulating layer or via a surface channel of the semi-conductor body of the same conductivity type as the polycrystalline channel. Zones of the elements may contact the buried zone A 2 directly. The polycrystalline channel 9 maybe formed simultaneously with the epitaxial layer 8 overlying the buried zone A 2 by the provision of a localized site on the prediffused zone A 2 which causes the material deposited thereon to form a polycrystalline structure. Such a site may comprise a thin layer of an alien material such as a dopant, or of suitably deposited Si. Where a dopant layer is used the dopant entering the deposited polycrystalline channel determines its conductivity type, although additional diffusion from the surface may also be employed, optionally for a sufficient time to cause the P-N junction between the channel 9 and the surrounding material to occur within monocrystalline material. The channel 9 may alternatively be formed by depositing a completely monocrystalline epitaxial layer 8 and then either vaporizing a selected area thereof with an electron or laser beam and vapour depositing polycrystalline material selectively into the resulting hole, or melting a selected area with an electron or laser beam, depositing an alien substance such as SiO 2 or a dopant on to the melted area, and cooling to resolidify, the presence of the alien substance causing polycrystalline formation. Fig. 5 shows a twolevel interconnection structure in which two buried layers A 1 , A 2 at different levels and of opposite conductivity types are connected to the surface by respective polycrystalline channels 3/10 and 9. The upper parts 10 of the former channels form during deposition of an upper epitaxial layer 8 as a result of the seeding action of the lower parts 3 of these channels already formed in a lower epitaxial layer 2. Dopant from the parts 3 diffuses into the parts 10, and may be reinforced by further diffusion from the surface. The surface-emergent areas of the channels 3/10, 9 are connected to the various elements of the integrated circuit.
GB4889671A 1970-10-27 1971-10-21 Integrated circuits Expired GB1327713A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2052714A DE2052714C3 (en) 1970-10-27 1970-10-27 Method for producing an integrated semiconductor device

Publications (1)

Publication Number Publication Date
GB1327713A true GB1327713A (en) 1973-08-22

Family

ID=5786291

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4889671A Expired GB1327713A (en) 1970-10-27 1971-10-21 Integrated circuits

Country Status (4)

Country Link
DE (1) DE2052714C3 (en)
FR (1) FR2111854B1 (en)
GB (1) GB1327713A (en)
NL (1) NL7114723A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2284189A1 (en) * 1974-09-03 1976-04-02 Radiotechnique Compelec Forming polycrystalline areas on substrate - using laser or electron beam preparing areas for epitaxial deposition

Also Published As

Publication number Publication date
DE2052714C3 (en) 1978-03-16
DE2052714B2 (en) 1977-07-21
FR2111854A1 (en) 1972-06-09
FR2111854B1 (en) 1977-01-28
DE2052714A1 (en) 1972-05-04
NL7114723A (en) 1972-05-02

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee