GB1322400A - Circuit design by an automated data processing machine - Google Patents
Circuit design by an automated data processing machineInfo
- Publication number
- GB1322400A GB1322400A GB2509370A GB2509370A GB1322400A GB 1322400 A GB1322400 A GB 1322400A GB 2509370 A GB2509370 A GB 2509370A GB 2509370 A GB2509370 A GB 2509370A GB 1322400 A GB1322400 A GB 1322400A
- Authority
- GB
- United Kingdom
- Prior art keywords
- function
- data processing
- circuit
- circuit element
- processing machine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
-
- G—PHYSICS
- G04—HOROLOGY
- G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
- G04C19/00—Producing optical time signals at prefixed times by electric means
- G04C19/04—Producing optical time signals at prefixed times by electric means by indicating members moved electrically, e.g. flap, band
Abstract
1322400 Data processing system TEXAS INSTRUMENTS Inc 26 May 1970 [11 June 1969] 25093/70 Heading G4A Starting with a known circuit having initial circuit element values, a function, depending on the sum, over a range of frequencies, of a power function of the difference between a specified performance characteristic and a synthesized performance characteristic, is evaluated, by a data processing machine which then modifies at least one of the circuit element values to improve the value of the function and allows the production of a representation of a modified circuit having an improved operating characteristic from which an actual circuit can be assembled, e.g. using a photomask. Derivatives of the function with respect to the circuit element values may also be generated, modification of circuit element value(s) depending on these derivatives as well as on the function itself. A list of possible functions is given in Table I in the specification.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US83389269A | 1969-06-11 | 1969-06-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1322400A true GB1322400A (en) | 1973-07-04 |
Family
ID=25265545
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2509370A Expired GB1322400A (en) | 1969-06-11 | 1970-05-26 | Circuit design by an automated data processing machine |
Country Status (3)
Country | Link |
---|---|
US (1) | US3622762A (en) |
CA (1) | CA924017A (en) |
GB (1) | GB1322400A (en) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4447881A (en) * | 1980-05-29 | 1984-05-08 | Texas Instruments Incorporated | Data processing system integrated circuit having modular memory add-on capacity |
US4495559A (en) * | 1981-11-02 | 1985-01-22 | International Business Machines Corporation | Optimization of an organization of many discrete elements |
US4613940A (en) * | 1982-11-09 | 1986-09-23 | International Microelectronic Products | Method and structure for use in designing and building electronic systems in integrated circuits |
US4580228A (en) * | 1983-06-06 | 1986-04-01 | The United States Of America As Represented By The Secretary Of The Army | Automated design program for LSI and VLSI circuits |
US4628471A (en) * | 1984-02-02 | 1986-12-09 | Prime Computer, Inc. | Digital system simulation method and apparatus having two signal-level modes of operation |
US4635208A (en) * | 1985-01-18 | 1987-01-06 | Hewlett-Packard Company | Computer-aided design of systems |
US5257201A (en) * | 1987-03-20 | 1993-10-26 | International Business Machines Corporation | Method to efficiently reduce the number of connections in a circuit |
US5047971A (en) * | 1987-06-23 | 1991-09-10 | Intergraph Corporation | Circuit simulation |
US4916627A (en) * | 1987-12-02 | 1990-04-10 | International Business Machines Corporation | Logic path length reduction using boolean minimization |
US4989132A (en) * | 1988-10-24 | 1991-01-29 | Eastman Kodak Company | Object-oriented, logic, and database programming tool with garbage collection |
JPH02189477A (en) * | 1989-01-19 | 1990-07-25 | Mitsubishi Electric Corp | Preparation of measurement specification for electronic circuit |
US5282148A (en) * | 1989-05-23 | 1994-01-25 | Vlsi Technology, Inc. | Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic |
US5113352A (en) * | 1989-06-20 | 1992-05-12 | Digital Equipment Corporation | Integrating the logical and physical design of electronically linked objects |
DE69032640D1 (en) * | 1989-09-05 | 1998-10-15 | Lsi Logic Corp | Logic compiler for designing circuit models |
US5497337A (en) * | 1994-10-21 | 1996-03-05 | International Business Machines Corporation | Method for designing high-Q inductors in silicon technology without expensive metalization |
US6301693B1 (en) * | 1998-12-16 | 2001-10-09 | Synopsys, Inc. | Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer |
US6282693B1 (en) * | 1998-12-16 | 2001-08-28 | Synopsys, Inc. | Non-linear optimization system and method for wire length and density within an automatic electronic circuit placer |
US7131097B1 (en) * | 2002-09-24 | 2006-10-31 | Altera Corporation | Logic generation for multiple memory functions |
US7260562B2 (en) * | 2003-06-30 | 2007-08-21 | Intel Corporation | Solutions for constraint satisfaction problems requiring multiple constraints |
US7254802B2 (en) * | 2004-05-27 | 2007-08-07 | Verisilicon Holdings, Co. Ltd. | Standard cell library having cell drive strengths selected according to delay |
US20050278659A1 (en) * | 2004-05-27 | 2005-12-15 | Xiaonan Zhang | Cell library providing transistor size information for automatic circuit design |
US7426710B2 (en) * | 2004-05-27 | 2008-09-16 | Verisilicon Holdings, Co. Ltd. | Standard cell library having cell drive strengths selected according to delay |
US7114134B2 (en) * | 2004-05-27 | 2006-09-26 | Veri Silicon Holdings, Co. Ltd | Automatic circuit design method with a cell library providing transistor size information |
US8347261B2 (en) * | 2009-09-10 | 2013-01-01 | Cadence Design Systems, Inc. | Method and system for implementing graphically editable parameterized cells |
-
1969
- 1969-06-11 US US833892A patent/US3622762A/en not_active Expired - Lifetime
-
1970
- 1970-05-26 GB GB2509370A patent/GB1322400A/en not_active Expired
- 1970-06-11 CA CA085249A patent/CA924017A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
CA924017A (en) | 1973-04-03 |
US3622762A (en) | 1971-11-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PE20 | Patent expired after termination of 20 years |