GB1317714A - Data handling systems - Google Patents

Abstract

1317714 Data transfer INTERNATIONAL BUSINESS MACHINES CORP 28 Jan 1971 3345/71 Heading G4A [Also in Division H4] A digital electric data handling system comprises units FU1, FU2 &c. joined by a common bus BS including duplicated data paths X, Y, the same data being transferred by alternate paths in successive transmissions so that inequality between the successive sets of data received indicates malfunction of the lines. Three FU's, FU1-FU3, e.g. memories, are connected to a common bus BS and thence to a data input 1L, e.g. a disc store. Each FU has two output registers, e.g. OR11, OR12 and two input registers, e.g. IR11, IR12, through one register can replace OR11 and IR11, or OR12 and IR12. The system preferably has a data path an even number of bits wide though spare lines may also be provided, especially if the system is constructed of monolithic circuits. Fig. 2 shows the output parts ORN1 and ORN2 of a unit FUN which is transmitting data to the input parts of unit FUM, via lines X, Y in bus BS. Data is transmitted down paths JK from ORN1 to IRM1 at time T1 and the same data is transmitted down paths J*K* from ORN2 to IRM2 at a later time T2 but with a particular bit travelling over line X at time T1 and line Y at time T2 and vice versa. This enables a faulty line to be identified by comparing the resultant contents of IRM1 and IRM2 in comparators C. Any mismatch causes an interrupt whereby the data can be resent, further error causing diagnostic operations. In a modification (Fig. 3, not shown) an extra line can replace either line X or line Y. The memory unit (Fig. 4, not shown) is divided into two identical halves from whence the bits for transmission down J, K, J*, K* come respectively. Also -included is a shift register, masking, and an arrangement for by-passing a faulty memory part using the spare lines and spare memory columns.