DE2203173B2 - Test device in an electronic data processing system - Google Patents

Description

Bits sent j * 3 Jk * Management function Y 1 Received bits O* 4th P * Comparison result P P k 1 1 X S. 1 P. 1 1 O O * 1 j 1 1 1 8th 8th 1 1 1 1 1 1 1 1 1 1 1 S. 1 1 O 1 1 O 1 1 1 1 0 1 0 0 1 1 O 1 1 1 1 1 8th 0 1 1 1 O 1 O 1 1 1 O 8th 8th T-H 1 1 O O 1 1 O 1 O 8th 8th 1 0 1 O 1 Ü 1 O 1 O 1 8th 1 1 O O 1 1 1 O 1 O 0 1 0 0 1 1 O O 1 O 1 O 8th 0 0 0 1 O 1 1 1 O O T-I 8th Cr ' 0 0 O 1 O 1 1 1 O 1 8th 8th 0 1 1 1 1 1 O 1 O 1 1 8th 1 1 O 1 O O O 1 O 1 0 1 0 0 O 1 1 1 O 1 O 1 8th 0 0 1 O O O O O 1 O O 8th 8th 0 1 O O 1 1
1 O O O O G 8th 0 0 1 O J
X O O O O O 1 8th 1 1 O O O 1 O O O O 0 1 0 0 O 1 1 O O O O O 8th 0 1 0 O O O 1 O O .. any « ¹ 8th 1 1 0 1 1 1 1 O .. any «* 1 O 0 1 1 ο 1 1 .. any " 1 1 0 ο ο 1 1 1 .. any O 0 1 O O 1 1 0 0 1

The table also shows that, when compared, the received data was correct in 24 of 36 cases appear:

a) There are four cases in which the lines work correctly;

b) There are eight cases where the lines do not work correctly but the data received do are correct, and

c) there are twelve cases where the lines work incorrectly and so do the received ones Data are wrong.

The cases mentioned under b) become evident when the transferred data changes, and up to errors in error detection are irrelevant. The cases mentioned under c) above seem being of a more serious nature, but in practice it turns out to be less likely, e.g. B. simultaneous errors in both lines. These cases can occur during normal error checking of the Data processing system are recognized. Therefore, line function errors can occur in the implementation the following test steps can be determined:

(i) Monitoring the comparison result inequality;

(ii) monitor the error indication during normal data processing;

(iii) Transmission of known data patterns and verification of the data actually received.

Step (i) can be carried out automatically by cross-connected comparators (o, o *; p, p *) and by ORing the results so that a signal is generated for each mismatch.

Step (ii) is a normal part of a data processing function, and a permanent error indication resulting from this step, without an error indication according to step (i), can identify malfunctions of the line according to class (c). In both cases, step (iii) will identify the fault. The real efficiency of the arrangement according to the invention becomes evident when many functional units are connected in the system at the same time, since in such systems the data can be transmitted from one unit to all the other units at the same time. It is assumed for this purpose that the units a, b, c and d are connected in this order. If the unit α then shows no error, but the units b, c and d, then quite a bit!

Security a line malfunction between the units α and b . However, if units a, c and d show no errors, only unit b shows a permanent error, then it is most likely that the error is in the connections of unit b to the manifold a very early step of a diagnostic operation, which input bit paths with certain! Output bit paths are connected. Not all of them

ö j units are connected to a special output bit path and there is also no reason why: the bit position identifier should be known in its entirety to the system (ie /, / * connected to u, « ^{! | of} the unit a, v, v * der Unit b and w, w * de:

Unit rf) this simplifies the diagnostic operations There where line function errors are recognized; there is also the option of either auto automatically or manually to patch in additional lines.

The data processing system shown in Fig. 1 consists of a number of functional units

I mean, of which only FUl, FU2 and FU'i are shown. These are via a common collective

, 1 line system BS with each other and with a data

> input IL connected. Each functional unit has

I _I two connecting paths leading to the manifold system and two connecting paths arriving from the manifold system. In the case of the functional unit

I FUl are these connecting paths through two exit

I output register OR 11, OT? 12 and two entry registers

I most IRIL and IR in the 12th Know this

I as duplicated or twin-one-Z output cgistCi

ί IRU plus ORU and IRn plus OR 12 considered

I will be. In this respect, this register arrangement represents a

I special feature than with some possible systems

^v | men output to and input from

■ j: Collective pipeline system via a joint regi-

3 ster for each possibility, d. i.e. that a

I register the functions of both IR 11 and OR 1 »

1 and a twin register the functions IR 12 and

I OR 12 executes.

I The data processing system basically has

1 a manifold system with an even number

t of lines, so that information with a straight line

I Number of bit positions in parallel in the input / output register

? also transmitted with this even number of bit positions

';' can be. However, special

5, lines or special bit positions are available,

i which are not used for the normal Dalenfh'8

; the (reserve lines, reserve bits, including those

for tax purposes). If a monolithic circuit technology is used, it is easier; hese

>, To ^ '- e to be incorporated during German manufacture, as

add them later. Hence came. uie the total number t of lines or bit positions that are effectively present

; are, even or odd sem.

- The reason for these twin-one-'-output-

i options are explained below with reference to FIG. 2

explained in more detail, which shows the outputs "of the functional unit FUN (N = 1, 2 ... h) ": id the input part: ■ of the functional unit FUM (M = 1. 2... / 1).

The figure has been compressed somewhat by revealing the functional units themselves. In this figure, the output part of the functional unit FUN is shown in such a way that it is in registration connection with the input part of the functional unit FUM.

The task of this arrangement is. To transmit data from one functional unit to another in such a way that correct operation of the transmission mechanism can be easily checked and, for example, faulty lines can be identified at least at their connection points. The basic mechanism of the check is based on transmitting the same data from ORNl to IRMi at time Γ1 and from ORN 2 to IRM 2 in time Γ 2, but with a certain bit in time Tl via a bit line and in time Γ 2 runs over a different bit line. A comparison of the content of IRM1 and IRM2 after time 72 then indicates whether or not there is an error.

The bit position j of ORN1 is connected to a line Y of the bus system. With this line the bit position are also connected ο of IRML, the bit position k * ORN of 2 and the bit position p * IRM 2. Similarly, the bit positions (same bits) and k ρ from ORNL and IRML and the bit positions / * and o * of ORN 2 and IRM 2 connected to line X of the common pipeline system.

Comparators c are switched on between the corresponding bit positions or registers IRM1 and IRM 2. Furthermore, T1 control lines are connected to ORN1 and IRM1 and r2 control lines to ORN 2 and IRM 2 .

There now follows from this that in the 21eit the Tl / bit over line Y of ORNL according IRML and the k-B'it migrates through the line X ORNL according IRML. Furthermore, in the time Γ2, the / * bit migrates via line X from ORN 2 to IRM 2 and the Ä * bit via line Y from ORN 2 to IRM 2.

Each unequal display of the comparators c at the end of the time T 2 causes an interruption in which, for example, the data is sent again, and if the error display is still present after this renewed transmission, further diagnostic operations can be initiated.

As already indicated, lines X and Y of the bus system can contain the (/, ä, o, p) bit positions of FUN and FUM and the (a, b, d, e) bit positions of FUS and FUE etc. (not shown ) combine in pairs. It is not necessary here for a specific bit position to relate to all other units, nor for a separate data path to be allocated to any unit for each Bi '. Another allocation of data paths and bit lines is given in FIG. 3, which shows only the input register of the functional unit FUr and the 0. 0 f 1 bit positions of this register. FIG. 3 is essentially the lower part of FIG. 2, where ρ - 0 1 and an additional line 5 of the collecting line are shown together with a locking system of AND gates (A) , by which line S can replace either line X or line Y. In addition, it will be apparent that parallel modifications to the output circuit of FIG. 2 are possible.

The bit position 0 of the input register IRr i is connected to the line Y of the bus via series-connected AND gates 10 and 12, which are each switched through by signals 71, which correspond to the time T \ , and Έτχ . This bit position is also connected to the additional line S of the bus via the AND gate 10 and the AND gate 13, which is switched through by a signal / rx . The bit position 0 + 1 of the input register IRrI is connected to the line Z of the bus via the AND gate 11, which is switched through by the signal Tl , and via the AND gate 14, which is switched through by the signal Ely. It is also connected to the line S via the AND gate 11 and the AND gate 15, which is switched through by the signal En. The bit position 0 * of the input register IRr 2 is similar to the line X of the bus via the AND gate 16, which is from the signal Γ 2, which corresponds to the time Γ 2, and the AND gate 14 and to the line S. connected via the AND gates 16 and 15. The bit position 0 + 1 * of the input register IRr 2 is connected to the line Y of the bus via the AND gate 17, which is switched through by the signal Γ 2, and via the AND gate 12 and the line 12 via the AND gates 17 and 13 connected.

Therefore, the input is usually from the

'69

Signals Π and T 2 controlled, which determine the two transmission cycles. Control also takes place via the Erx and ETy signals.

In this illustration, this circuit essentially corresponds, as far as its function is concerned, to the lower half of FIG. 2. If the line X is to be replaced by the line 5 as a result of detected line function errors , the signal ΈΤχ is replaced by the signal Erx . Similarly, when line Y is to be replaced by line S , signal ETy is replaced by signal Ery . It must be taken into account here that the function of the circuit disappears when the line S replaces the two lines X and Y at the same time.

This is how it is in FIG. 1 if the unit has input circuits in F i g. 3 contains the type shown along with parallel output circuits, capable of, most of them Detect line malfunctions by transferring the same data via crossed connection paths in consecutive cycles. It is also able to get through a faulty line to replace an additional line.

1 sheet of drawings 409521/328

Claims (3)

Error display if an inequality is detected. Electronic data processing systems with re 1. Equipment for testing transmission and redundant functional units are on Reception modules one of at least two 5 known (cf. magazine "Automatic Control", De redundantly operating functional units December 1959, pp. 46 to 52, in particular Fig. 5), si < existing electronic data processing systems, however, use a test system that determines * system, including those connecting them, from errors on which the redundant units connect several Lines existing collecting lines cannot recognize lines. conditions for errors in which, irrespective of io, errors in the information value cannot be present even in the case of a coding arrangement with information transmitted via the 2IU, which is always described on a line in the German Auslegeschrifi fangsbaugmppe a fixed 1061 834, through redundant in-bus lines and input-Z-output circuits of information transmission with subsequent control functional units of an electronic data comparison of the received information, whereby 15 processing systems are recognized,
if they are the same, an error signal occurs, because under the same deficiency there is also a Verdure h marked that two bits go to the signal transmission, which is explained in the (/, k; Fig. 2) of the first output register German Auslegeschrift 1290 960. (ORNl) of the first functional unit (e.g. FUN) Even with this method it is not possible to transfer a large number of error categories in a data (YX) to the corresponding bit positions ( YX) via a line pair 20 at a first time (Tl) o, p) of the processing system to determine how it was initially shown in the first input register (IRMl) of the second. Functional unit (z. B. FUM) and then to The invention therefore has the task of providing a second time (T2), the corresponding provision of a device with the help of which redundant bits (/ *, k *) from the second off - 25 send and receive modules of a redungangsregister (ORN2) of the first functional unit working on the same pair of lines, but with the electronic data processing system including the reverse of the first transmission of the bus lines connecting them to the assignment of the lines (Z, Y) to the to check such errors in which, regardless of the speaking bit positions (o *, p *) of the second em- 30 of the information to be transmitted in the receive output register (IRM 2) of the second function module, a fixed information unit is always transmitted on one line , which is applied after the tion value has taken place, regardless of which information is transmitted by the comparator (c) the second time was transferred in. the E. input registers to the corresponding to each other. The object of the invention is achieved by the corresponding places stored bits to equality 35 in the claims specified features,
to be checked. In this way the advantage is achieved once 2. Test device according to claim 1, characterized in that certain errors, which are characterized by the known that the state of the art transmitted simultaneously in such systems could not be fixed bit positions (/, k or / *, k *) arbitrary positions 'Now in the error checking'<ng distance from each other. 40 can be included and that on the other hand 3. Test device after one of the previous and the redundant lines in addition to the paring line Claims, characterized in that the transmission of useful information is used any transmission path for the bit position pairs can be det. (/, / '*; k, k *; o, o * and p, p * \ F ig. 2) with each Line of the line pair (XY) and with an additional collecting line (S; F i g. 3) described in more detail with reference to the drawing. It shows via adjustable interlocking circuits (13, Fig. 1 is a block diagram of part of the two 12; 14, 15) is connected, whereby by a repetitive arrangement, configuration of the lock settings. 2 is a block diagram with further individual healing circuits some or all of the lines of the 50th of the system of FIG. 1, Line pair (Z, Y) from part of the line F i g. 3 the block diagram of a further development lines of the common additional manifold of the in F i g. 1 illustrated system,
can be replaced. To explain the mode of operation of the example The following table is used for a specific arrangement: 55 in the table below means a 1 in the column »comparison result« equality and The invention relates to a device for checking a 0 inequality, while in the column "Line checking of transmitting and receiving modules of a function" g means that the line is working correctly or 0 was received, electronic data processing units existing 60 depending on what was sent. This last processing system, including the possibility to connect it, is a valid possibility, as the collective one bit, which consists of several lines, normally from a register bit position lines to errors in which the information to be transmitted occurs independently and enters another register position In the reception and the possible sources of error, register errors, the receive module on a line must always include a fixed information such as line error, with such a formation value being applied. A redundant error can be temporary or permanent, information transfer with subsequent information transfer. You only need to be represented in the table in the column »Inherent information received is a service function«.