DE2203173A1 - Electronic data processing system - Google Patents

Description

Boeblingen, January 21, 1972 yo-fr / we

Applicant: International Business Machines

Corporation, Arinonk, N.Y. 10504

Official File number: New registration

Applicant's file number: Docket UK 970 005

Electronic data processing system

The invention relates to an electronic data processing system, in which certain data paths are subject to a special check.

The invention relates in particular to the testing of certain data paths such electronic data processing systems, the structure of which is based on functional storage units. The essentials The feature of these function storage units is that they contain function tables which are necessary for the implementation arithmetic and logical operations can be used. Such function storage units are for example in the British Patents 1,127,270 and 1,186,703.

The object of the present invention is now to provide a simple and advantageous test arrangement for testing those Data paths that are used for bit transfer between the memory cells and the input / output registers of the memory arrangements are provided.

For an electronic data processing system, the invention consists in that in each case at least two functional units are provided, the double data connection paths for each

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Have connection of the functional units and that also a. common manifold system and facilities for the alternating Use of the data paths of each unit are provided for the transmission of the same data between the units, the arrangement being constructed in such a way that a pair of bits in a first transmission (in time T1) over a first bit path to a second bit path and the same bit pair in a second transmission (in time T2) via a third bit path to one fourth bit path is transmitted, whereby an erroneous transmission due to a defect in the bus lines due to the inequality of the bits received on the fifth bit path and / or by an inequality of the bits received on a sixth bit path is marked.

Further features, advantageous configurations and developments the subject matter of the invention can be found in the subclaims.

The invention thus achieves the advantage that certain, above-mentioned data paths of an electronic data processing system can be checked for any existing defects in a very simple and reliable manner. The following will the invention is described in more detail with reference to an embodiment illustrated by drawings. Show it:

Fig. 1 is a block diagram of part of the invention

moderate arrangement,

Fig. 2 is a block diagram showing further details

of the system according to FIG. 1,

3 shows the block diagram of a further development of the

system shown in Fig. 1,

Fig. 4 is a block diagram of a function memory unit, the system illustrated in in Fig. 1

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can be used.

Fig. 5

the block diagram of a modified device according to FIG. 4,

Fig. 6

the block diagram of a further part of the modified function memory unit according to Claim 4 and

Fig. 7

the block diagram of a further modification of the function memory unit according to FIG.

The following table is used to explain the mode of operation of the arrangement according to the invention:

sent j * k * Line Y O received O* P * Comparison P P * Bits 1 1 function G 1 Bits 1 1 Result 1 j k 1 1 X G r-l P. 1 p-l O O * 1 1 1 1 1 G G 1 1 O 1 1 O 1 1 1 1 1 1 1 1 i-l 1 1 1 1 1 1 1 0 0 0 0 1 O O O 1 1 1 O G G 1 1 1 O 1 1 1 1 1 O G G r-l 1 1 O O O 1 O 1 O G G 1 0 O O 1 1 1 O 1 O 1 1 1 1 1 1 1 O 1 O 1 O 0 0 0 0 1 O O 1 1 O O 1 G G 0 0 O 1 1 1 1 O O 1 G G 0 0 1 1 O 1 O 1 O 1 G G 0 1 O f-l 1 O O 1 O 1 1 1 1 1 O 1 O 1 O 1 O 1 0 0 0 0 O O 1 O O 1 O O G G 0 1 O O O r-l O 1 O O G G 0 1 1 O 1 O O O O O G G 0 0 O O 1 1 O O O O 1 1 1 1 O r-l O O O O O O 0 0 0 0 O O r-l 1 O O .any. G i-l 1 0 r-l i-l O 1 O O .any. G 0 1 0 1 O 1 1 . .any. i-l 1 0 1 O 1 1 1 .any. 1 0 0 0 O O 1 1 O 1 1 • 0 0 1

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In the table above, a 1 in the "Comparison result" column means equality and O means inequality, while in the "Line function" column g means that the line is working correctly and 1 or O means that a 1 or O has been received, depending on what was broadcast. This latter possibility is a valid possibility because a bit usually consists of a Register bit position exits and enters another register position. Furthermore, the possible sources of error must be register errors as well as line faults, such faults being temporary or permanent, they just have to be represented in the table in the "Management function" column. The table also shows that the received data appear correct in 24 of 36 cases when compared:

(a) There are four cases in which the lines work correctly;

(b) There are eight cases where the lines do not work correctly but the data received is correct and

(c) there are twelve cases in which the lines operate incorrectly and also the received data is wrong.

The cases mentioned under b) become obvious if the transferred data change and errors in the Error detection does not matter. The cases mentioned under c) above seem to be of a more serious nature, but in practice it appears that that they are less likely, e.g. simultaneous faults on both lines. These cases can occur during normal Error checks of the data processing system are detected. Therefore, conduction malfunctions can occur in the implementation the following test steps can be determined:

(i) monitoring of the comparison result inequality; (ii) monitoring of error indication during normal data processing;

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(ill) transmission of known data patterns and verification of the actual received data.

Step (i) can be carried out automatically by means of cross-connected comparators (o, o *; p, p *) and by means of an OR link of the results so that a signal is generated for each mismatch.

Step (ii) is a normal part of a data processing function, and a permanent error indication resulting from this step without an error indication according to step (i), can detect malfunctions of the line according to class (c). In both cases, step (iii) will identify the fault. The real efficiency of the arrangement according to the invention becomes evident when many functional units are simultaneously are connected in the system, since in such systems the data from one unit to all other units at the same time can be transferred. It is assumed that the units a, b, c and d are connected in this order. If the unit a then shows no error, but the Units b, c and d, then there is almost certainly a conduction malfunction between unit a and b. if however the units a, c and d do not show any errors, but only the unit b shows a permanent error then it is most likely the fault is in the connections from unit b to the bus. In addition, it is immaterial to know, at least in a very early step of a diagnostic operation, which input bit paths with certain output bit paths are connected. Since not all units are connected to a particular output bit path and neither are they There is reason why the bit position identifier should be known in its entirety to the system (i.e. j, j * connected to u, u * der Unit a, v, v * of unit b and w, w * of unit d) this simplifies the diagnostic operations.

There are where line function faults can be recognized

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also the possibility of either automatic or manual additional lines to patch in.

Normally, the data flow path of such a system will be designed for the parallel transmission of an even number of bits, so that all of the bit positions in the data flow path can be "erit paired" in this manner. Further details are shown in Fig. 1.

The data processing system shown there consists of a number of functional units, of which only FU1, FU2 and FU3 are shown. These are via a common manifold system BS connected to one another and to a data input IL. Each functional unit has two to the manifold system leading and two arriving from the manifold system. In the case of the functional unit FUl are these connection paths through two output registers ORIl, ORl2 and two input registers IRIl and IR12. These can be used as duplicated or twin input / output registers IRIl plus ORIl and IR12 plus 0R12 can be considered. This register arrangement is a peculiarity insofar as in some possible systems the output to and the input from the Bus system can be done via a common register for each possibility, i.e. that one register the functions both of IRIl and ORIl and a twin register the functions IR12 and 0R12 executes.

The data processing system basically has a manifold system with an odd number of lines, so that information with an odd number of bits is parallel to the Input / output registers can also be transferred with this odd number of bit positions. However, special lines can also be used or special bit positions that are not used for normal data flow (reserve lines, Reserve bits, including those for tax purposes). When a monolithic circuit technology is used, it is easier to

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incorporate these additives during manufacture rather than adding them later. Therefore, the total number of lines or bit positions that are effectively present can be odd or even.

The reason for these twin input / output options is explained in more detail below with reference to FIG. 2, which shows the output part the functional unit FUN and the input part of the functional unit FUM are shown. The figure was compressed a bit by adding the Functional units themselves have been omitted. In this figure, the output part of the functional unit FUN is shown in such a way that it is in registration connection with the input part of the functional unit FUM.

The task of this arrangement is to receive data from a functional unit to transmit to the other so that a correct operation of the transmission mechanism is easily checked and, for example faulty lines can be identified at least at their connection points. The basic mechanism the check is based on transferring the same data from ORNl to IRMl at time T1 and from ORN2 to IRM2 in time T2, however, a certain bit runs over a bit line in time T1 and over another bit line in time T2. A comparison of the content of IRM1 and IRM2 after time T2 then indicates whether or not there is an error.

The bit position j of ORNl is with a line Y of the bus system tied together. The bit position ο of IRMl and the bit position k * of ORN2 are also connected to this line and the bit position p * of IRM2. Similarly, the bit positions (equal to bit positions) are k and ρ of ORNl and IRMl and the bit positions j * and o * of ORN2 and IRM2 are connected to line X of the bus system.

Comparators c are switched on between the corresponding bit positions or registers IRM and IRM2. There are also Tl control lines with ORNl and IRMl and T2 control lines with

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ORN2 and IRM2 connected.

It now follows from this that in the time Tl the j-bit over the Line Y should migrate from ORNl to IRMl and the k-bit over line X from ORNl to IRMl in time T2. Further should the j * bit migrates over the line X from ORN2 to IRM2 and the k * bit over the line Y from ORN2 to IRM2.

Each unequal display of the comparators c at the end of the time T2 causes an interruption in which, for example, the data is renewed sent and if the error display is still present following this renewed transmission, further diagnostic operations can be initiated.

As already indicated, lines X and Y of the bus system can have the (j, k, o, p) bit positions of FUN and FUM and combine the (a b d e) bit positions of the FUS and FUE etc. in pairs. It is not necessary here that a specific Bit position connected to all other units, nor that any unit has a separate data path for each bit is allocated. Another allocation of data paths and bit lines is given in Fig. 3, which is only the input register of the functional unit FUr and the 0, 0 + 1 bit positions of this register. Fig. 3 is essentially the lower part of Fig. 2, where ρ = 0 + 1 and an additional line S of the collecting line together with an interlocking system of AND gates (A) by which line S can replace either line X or line Y. In addition, it is Obviously, parallel modifications to the output circuit of Fig. 2 are possible.

Bit position 0 of the input register IRrI is with the line Y of the collecting line via AND gates 10 and connected in series 12 connected, which are each switched through by signals Tl, which correspond to the time Tl, and Erx. This bit position is also with the additional line S of the collecting line via the AND

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Gate 10 and the AND gate 13 connected, which is switched through by a signal Erx. The bit position 0 + 1 of the input register IRrI is connected to the line X of the collecting line via the ÖND gate 11, which is switched through by the signal Tl, and via the AND gate 14, which is switched through by the signal Ery, connected. It is also connected to the line S via the AND gate 11 and the AND gate 15 connected, which is switched through by the signal Ery. The bit position 0 * of the input register IRr2 Is in a similar way with the line X of the collecting line via the AND gate 16, which from the signal T2, which corresponds to the time T2, and the AND gate 14 and connected to the line S via the AND gates 16 and 15. The bit position 0 + 1 * of the input register IRr2 is connected to the line Y of the bus via the AND gate 17, which is switched through by the signal T2, and via the AND gate 12 and the line 12 via the AND gates 17 and 13.

Therefore, the input is normally controlled by the signals T1 and T2, which determine the two transmission cycles. One Control also takes place via the Erx and Ery signals.

In this representation, this circuit essentially corresponds, as far as its function is concerned, to the lower half of FIG. If the line X is to be replaced by the line S as a result of established line function errors, this will be Signal Erx replaced by signal Erx. Similarly, if line Y is to be replaced by line S, the Signal Ery replaced by Signal Ery. It must be taken into account here that the function of the circuit disappears if the line S replaces the two lines X and Y at the same time.

In this way, the system shown in Fig. 1 is when the unit is input circuits of the type shown in Fig. 3 together with parallel output circuits, able to Most line malfunctions can be identified by the same data being crossed in consecutive paths Cycles are transferred. It is also able to

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to replace a faulty line with an additional line. If more additional lines and more interlocking circuits and controls are available, a more complicated replacement operation is necessary, although this is kept in mind must that an increase in circuit components not only the cost, but also the risk of errors increases, so that an unlimited number of additional lines does not make sense is what it initially appears.

The functional units FU1, FU2, FU3 can be functional storage units, as described, for example, in British patents 1,127,270 and 1,186,703. The general embodiment of such a unit is shown in Fig. 4, with a bit position connected to the X, Y lines of the bus system. Also in this figure are the Additional line S and the charging device IL are shown. It is also assumed that the arrangements of FIG. 2 or 3 also should be present, although they are not shown in FIG.

The function memory unit has twin arrangements 20 and with memory cells that can assume four states (1 = 01, 0 «10, X« 00, Y = 11), further twin input registers 22, 23, Twin input mask registers 24 and 25, twin output mask registers 26 and 27, twin output registers 28 and 29 and finally an adaptation mask register 30 which is common to both arrangements. Furthermore, many other features are and Parts are present, including the control circuit, which are not shown here. The two characteristics of particular importance for the present invention, the comparators C (only one of which is shown at the input and one at the output) and the shift register 31 which has a serial input from the auxiliary line S and finally a serial output to it the line Q and parallel outputs to both input registers 22 and 23 has.

Because of the double structure of the functional storage unit, it offers

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very well suited for use in the arrangements of the present Invention. Your structure becomes a definite one Tent either one or the other half of the unit used and the same data is stored in each arrangement, so that the cycles T1 and T2 are included in the structure of the function memory unit. The tables that form the working basis of the function memory unit (patterns of 10 (0) 01 (1) and 00 (X) are sent via the auxiliary line S and the shift register 31 input from the loading device IL, which can be, for example, a disk storage device. With this arrangement it is possible read out the contents of the input register on line Q by using the shift register 31 "in reverse". This is done during step (ill) of the line malfunction diagnosis, as mentioned above.

Another important aspect that emerges from that shown in FIG Function storage unit results, is in the additional column 32, 33 in each arrangement and the corresponding additional bit positions 34, 35, 36, 37; 38, 39, 40, 41 in each mask register 24, 25, 26, 27, furthermore in each input register 22, 23 and in each output register 28, 29. The register bit positions 38, 39, 40, 41 are connected to the additional line S and not connected to load shift register 31. This facility makes it possible to bypass a defective part by the additional line S and the additional columns 32 and 33 are used, the content of the columns assigned to the error being transferred to the additional columns and by the mask register accordingly is set.

During normal operation of the unit, parts 32 to 41 do not exist as far as the system is concerned, as the columns 32, 33 are empty and bit positions 34, 35, 36, 37 contain output mask bits. When a column shift is required is, and in the worst case scenario, only one array can be assumed to contain the correct data to be moved should, for example, the column 42 in the arrangement 20, wherein

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if your twin contains 43 incorrect data, the following steps are carried out:

(1) With the cells of the auxiliary columns set to S - 11 (y) the cells of column 42 are searched for a pattern 10 (0) and a marker is placed in the marker register Enter 30 for each cell that responds (cells containing 10 (0) and 00 (X)). Then a zero is entered in the cells on the right in column 32, according to the markings;

(2) the cells of column 42 are searched for a pattern 01 (1) and a marker is entered into marker register 30 for each cell that is addressed (that is, Cells that contain 01 (1) and 00 (X). Then a 0 is entered in the cells on the left in column 32, according to the markings. It should be noted here that column 32 is now an exact copy of the correct Contains data in column 42.

(3) The content of the arrangement 20 is written into the arrangement 21 and the masking is reset to the deleted positions 34, 35, 36, 37 and to the exit marker columns 42, 43 with positions 44, 45, 46,

These replacements are not exactly equivalent to replacing a line of the manifold, but in this way certain are made overcome hard errors in the circuit and allow the system to continue processing data. More additional columns obviously also allow more column shifts to take place, but this also requires more extra lines. This also includes more circuitry, a more difficult system representation for diagnostic purposes, and a higher risk as to Circuit malfunctions because the system also contains more circuits.

It should be mentioned again that it was assumed as an example that in the circuit of FIG. 4, the selective circuit shown in FIG Coupling is used. For example, the additional column can be selectively

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_ 13 -

connected to all bit positions of the input / output options as well as the additional line, so that the interlocking circuits of the additional column or the additional column are reconfigured plus the additional mask bit position plus the additional input / output options bit position the faulty column or the faulty column plus the faulty mask bit position plus which can replace faulty input / output bit positions.

Finally, it is possible to arrange the function memory unit in such a way that that they can be used as a twin arrangement (duplex operation) or as a single arrangement or as a variant of individual arrangements (simplex operation) can work.

Part of the circuitry of a function memory unit, as shown in FIG represent the j * column of a function storage unit. It is not difficult, in particular, to identify the remaining parts of the circuit according to FIG. 1 with respect to the other figures, since the arrangement of the parts in the circuit according to FIG. 5 is designed so that the greatest possible flexibility in operation results. The bus lines X and Y are shown in FIG. Referred to and the details 54 and 61 are largely the Registerbitpositionen, the j columns, k, j *, k * of the one-ZAusgangsmöglichkei- th in accordance with the preceding figures, except that, for example, the bit position 54 can be used to transfer a bit from either a bus X, Y to the columns 50 and / or 53 or from these columns to one of the buses. Thus, items 118, 120, 122 and 124 are read circuitry arranged to respond to signals on the buses to which they are connected and accordingly set the register positions that are allowed to set while items 119, 121 , 123 and 125 are driver circuits arranged to respond to the register positions to which they are responsive

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allowed and that they exercise the driver function for the bus lines to which they are connected accordingly. Access to each register position can be obtained from any group of three of ports 62, 63, 64; 69, 70, 71; 76, 77, 78; 83, 84, 85; 90, 91, 92; 97, 98, 99; 104, 105, 106; 111, 112, 113. Furthermore, each register bit position can transmit its contents via one of the following groups of four of gates: 65, 66, 67, 68; 72, 73, 74, 75; 79, 80, 81, 82; 86, 87, 88, 89; 93, 94, 95, 96; 100, 101, 102, 103; 107, 108, 109, 110; 114, 115, 116, 117. Each of the gates 62 to can be switched through separately from a signal on a control line, the control lines for each gate being designated by a short line ending with a circle. The control signals are identified with the associated gate number with a preceding c. 5 also shows the connections between the gates.

If the reading circuit 118 is viewed, it is evident that a bit on the bus Y in each of the bit positions 54, 55, 56, 57 via the gates 63, 70, 78, 85 in the presence of the corresponding control signals c63, c70, c78 , c85 can be entered. A bit on the bus X can be entered via the read circuit in each of the bit positions 54, 55, 56, 57 via the gates 64, 71, 77, 84 when a corresponding control signal c64, c71, c77, c84 is present. Similarly, a bit on bus Y in each of bit positions 58, 59, 60, 61 via gates 91, 98, 104, 111 and a bit on bus X in each bit position 58, 59, 60, 61 via the Gates 90, 97, 105, 112 from either the reading circuit 122 or the reading circuit 124 can be input.

From each of the bit positions 54 to 61, a bit can be sent to the bus Y via the gates 67, 74, 82, 89, 94, 101, 107 or 114 when the driver circuits 119 or 123 are used. Furthermore, a bit can also be sent via the gates 68, 75, 81, 88, 93, 100, 108 or 115 are transferred to the collecting line X, when the driver circuits 121 or 125 are used.

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From each of the bit positions 54 to 61, a bit can be sent to the bus Y via the gates 67, 74, 82, 89, 94, 101, 107 or 114 when the driver circuits 119 or 123 are used will. Furthermore, a bit can also be transmitted to the bus X via the gates 68, 75, 81, 88, 93, 100, 108 or 115, when the driver circuits 121 or 125 are used.

The remaining intertor compounds fall into four, essentially identical groupings, and only one of these groupings will Considered in detail below, with a bit transfer to and from columns 50 and 53 and bit positions 54 and using gates 62, 65, 66, 83, 86, 87. The other three groupings can be identified by the details 50, 53; 58, 61? 92, 95, 96; 113, 116, 117; furthermore 51, 52; 55, 56; 69, 72, 73; 76, 79, 80 and finally through 51, 52; 59, 60; 99, 102, 103; 106, 109, 110 can be specified.

Column 50 can enter a bit in bit position 54 via the gate and a bit from bit position 54 via gate 66 and / or record from bit position 57 via gate 86. Similarly, column 53 can place a bit in bit position 57 Enter via gate 83 and a bit from bit position 57 via gate 87 and / or from bit position 54 via gate 65 received. This means that the OR function (content 54 · output 53) and can be used with regard to bit position 57. The function (content 57 output 50) can also be generated and applied with respect to bit position 54. This application occurs in both cases (Output 50 · Output 53) by entering output 50 in bit position 54 or output 53 in bit position 57, which may be earlier. It will be summarized again in the following, which functions are shown in FIG Circuit is able to carry out:

a) Each bit position can be set so that it takes the bit from both buses X

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or Y contains;

b) each bit position can be the driver function with respect to both bus lines X or Y. carry out;

c) (j * j *) can be generated in the unit and with respect to each of the bit positions 54, 57, 58, 61 can be applied without the use of any X or Y lines;

d) in a similar way, the function (k · k *) with respect to each of the bit positions 50, 56, 59, 60 are applied;

e) each of the two columns 50 or 5 3 can have an input from each bit position 54, 57, or 61 received;

f) each of the two columns 51 or 52 can have an input from each bit position 55, 56, or 60 received;

g) the function (content 54 · content 57) or (content 58 · content 61) can be entered in column 50 or 53 can be entered;

h) the function (content 55 · content 56) or (content 59 · content 60) can be in column 51 or can be entered and

i) Column 50 can be in bit positions 54 or 58, column 51 in bit positions 55 or 59, column 42 in bit positions 56 or 60 and column 5 3 in bit positions

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- 17 -sitions 57 or 61 can be issued.

Such a unit can have an input from both pairs of Receive lines X and Y and output information to both pairs of lines X and Y. These possibilities are not considered further in the following, since the assumption is made is intended to be input through read circuits 118 and 120 and output through driver circuits 123 and 125 target. In normal operation as a twin arrangement with the twin cycles and arrangements for data transmission via crossed bus lines, the following procedure is used:

In the first cycle (T1), bit position 54 is received from bus Y via read circuit 118 and gate 63 if present of the control signal c63 and the bit position 56 from the bus X via the read circuit 120 and the gate 77 with the simultaneous presence of the control signal c77 and a search operation with respect to both arrangements in the presence of the Control signals c65, c66, c79, c80 are initiated on the assumption that the received data are correct.

In the second cycle (T2) the bit position 55 is filled by the bus Y in the presence of the control signal c70, wherein the read circuit 118 is used. The bit position 56 is present in the same cycle from the bus X here of the control signal c77 filled using the read circuit 120.

A comparison of the content of bit position 54 with the content of the Bit position 57 and the content of bit position 55 with the content of bit position 56 are then carried out. If a mismatch is found, the search that has already started is stopped. The comparators that this Carry out a comparison are not shown in FIG. 5. Diagnostic operations are then initiated and if the actual content of bit positions 54 to 57 is required,

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it is output twice from the X and Y lines at the same time by using the driver circuits 119 and 121 when the control signals c67, c81, c74, c88 are present at the same time. However, since the content of each bit position 54 to 57 can be detected by both lines X and Y, depends on the use of a certain control signal from group c67, c68, c74, c75, c8l, c82, c88, c89 depend on which content is required on which bus and at what time. This is a function of the content or structure of the unit that controls the diagnostic operation, which is not important in this context.

If no mismatch is found, the search results may be in bit positions 58-61 when the control signals c92, clO6 are present, which are followed by c99 and el13, and these are transferred to lines X, Y is transmitted in the twin cycles using driver circuits 123 and 125. The control signals c 94 and clO8 appear in the first cycle (Tl) and the control signals el15 and ClOl in the second cycle (T2). If only an arrangement the unit is to be used, for example if the other unit is defective, then the twin input and output cycles can still be used with the data transmission over the largest bus, it does not matter which one Arrangement is used. Assume now that columns 50 and 52 are to be used. For this purpose, the bit positions 54 and 56 are filled and a search is initiated, with only the control signals c66 and c80 are used. Bit positions 55 and 57 are filled in cycle T2 and a comparison is made is carried out. The search is stopped or carried out as before, but this time only with regard to columns 50 and 52. The results are entered in bit positions 58 and 60 when control signals c92 and cl06 are present. Then, when the control signals c 96, cll3 and cllO, c99 the content of bit positions 58 and 60 in bit positions 91 and 59 is doubled, so that the implementation of a normal

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Output cycle is possible.

If the columns 5O, 52 and 53, 51 are different tables for example, if the unit is used as a unit of double capacity but without duplication, then is it will be apparent that the inputs filling bit positions 54 through 57 will be the same as we were before. In this In the case where only one marker register is used, as shown in FIG. 4, the one arrangement is searched first and then the other, the output information being derived as in the case where there is only one arrangement was used, but with the generation of output information only when both searches have been carried out. With two marker registers, one for each arrangement, a simultaneous search is also possible.

In all of the aforementioned cases, there was only one match assumed, so that only one output information is obtained for each complete search process. It can, however there are also multiple matches for each search process, with the results of the matches then over an OR function must be combined. In this case, these OR functions, regardless of the type in which the Unit used is created by selectively using gates 92, 95, 96, 99, 102, 103, 106, 109, 110, 113, 116 and 117 will. If an arrangement (columns 51 and 53) is not searched, then the output information of column 50 can, for example can be combined according to an OR function if the control signals c92 and c95 are present together for each output. If both arrays are searched, one array is read out into bit positions 58-61 before the other. the Columns 50, 52 are read out as often as necessary. The OR functions are generated as before. After that, the Columns 51, 53 read out repeatedly as often as necessary. There are two different types of processing at this stage. Either the control signal c96 can be used during the first readout

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appear with cll3 and cll6 and cllO with c99, clO2, which are consecutive can be linked according to an OR function. There can also be c99, clO2, cll3 and cll6 alone, in which If the output information of the columns 51, 53 is then simply brought into the bit positions 59 and 61 after an OR function will. After the occurrence of c96, el13, cll6, c99, clO2 and c 110 a total OR function is generated and related of bit positions 59 and 61 are applied. In both cases the OR function is generated and with respect to the bit positions 59 and 61 applied. This can be done in bit positions 58 and 60 when the control signals c92, c95, cll7, cl03, clO6 and c109 are duplicated. It is obvious that the OR function also generated and applied with respect to bit positions 58 and 61 and duplicated in bit positions 59 and 60 will.

The circuit in Fig. 6 is essentially the same as the circuit in Fig. 5, with only the gates 64, 68, 72, 78, 82, 86, 90, 93, 103, 104, 107 and 117 are missing and consequently the functions that depend on these gates are also missing, what remains is the twin cycle transfer in the case of crossed manifolds, if the arrangement works as a doubled arrangement and if both arrangements can be used as a unit of double size without duplication, although the OR function only generates and relates to bit positions 59 and 61 (or 55 and 57) can be applied so that the control signals el14 and clOl at the T1 gate output time and el15 and clOO at the T2 gate output time for the transmission of the OR function appear.

However, if you are only working with an arrangement defined by 50, 52 and the bit positions 58, 60, then this is it Twin cycle transmission characteristic of the crossed manifold due to the absence of the gates 93 and 107 not given, since the OR function by the simultaneous connection of two Bit positions must be reached on a bus, which leads to errors, for example as a result of interference signals, so that this is repeated and does not appear as an error.

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The In Flg. 7 essentially corresponds to the circuit shown the circuit according to Flg. 6, although gates 71, 75, 85, 89, 97, 100, 111 and 114 and the corresponding functions dependent on these missing gates are missing.

In this crossed manifold arrangement, there is one Twin cycle transfer is only possible if the unit is with double arrangements works and still both positions of each pair or no position of a pair are the only possibilities to be output from the system by mask, whereas in the circuits according to FIGS. 5 to 6 one such restriction does not exist. Therefore, all circuits according to FIGS. 5, 6 and 7 in the system of FIG. 1 can be replaced. But as the circuits get simpler and therefore also cheaper, the functions that can be derived from these circuits will also be less diverse.

209833/1 US

Claims (11)

- 22 - PATENT CLAIMS l7) Electronic data processing system, characterized in that at least two functional units (FUl, FU2; Fig. 1) are provided, which each have double data connection paths for connecting the functional units and that also a common bus system and facilities (ORIl, OR12, IRIl, IR12) for the alternating use of the data paths of each unit for a transmission of the same data between the Units are provided, the arrangement being constructed in such a way that a pair of bits in a first transmission (in time T1) via a first bit path (j, k, Y, X; Fig. 2) to a second bit path (o, p) and the same Bit pair is transmitted in a second transmission (in time T2) via a third bit path (j *, k *, X, Y) to a fourth bit path (u *, p *), whereby an incorrect transmission due to a defect in the busbars ( X, Y) due to the inequality of the received bits on the fifth bit path (o, o *) and / or by an inequality of the bits received on a sixth bit path (p, p *). 2. Electronic data processing system according to claim 1, characterized in that j = ο and k = j + r. 3. Electronic data processing system according to claim 2, characterized in that r = 1. 4. Electronic data processing system according to one or more of claims 1 to 3, characterized in that that comparators (c; Fig. 2) are arranged between each input bit path (o; o *) and (p, p *). 5. Electronic data processing system according to claim 4, characterized in that the comparator (c; Fig. 2) 209833/1 UB of each functional unit are interconnected (Fig. 2) and provide an output signal when there is a mismatch the information attached to their inputs. 6. Electronic data processing system according to one or more of claims 1 to 5, characterized in that each bit path (j, j *; k, k ^x ; o, o * and p, p *; Fig. 2) with each of the busbars ( X, Y) and is connected to a common additional bus line (S; Fig. 3) via adjustable interlocking circuits (13, 12; 14, 15), whereby some or all of the busbars (X or Y) of some of the lines of the common additional manifold can be replaced. 7. Electronic data processing system according to an or ^v several of claims 1 to 6, characterized in that the functional units (FUi; Fig. 1) are functional storage units (Fig. 4) with twin arrangements of multi-state storage cells and that furthermore a loading device (IL) for loading function tables into the functional storage units is provided via the common manifold system. 8. Data processing system according to claim 6, characterized in that that the functional units (FUi; Fig. 1) functional memory units with twin arrangements of multi-state memory cells (Fig. 4) and that a loading device (IL) for loading function panels into the Function storage unit via the common additional manifold (S) is provided. 9. Electronic data processing system according to claim 7 or 8, characterized in that a device 209833/1 Ηδ (26, 27; FIG. 4) are provided for masking the outputs of the selected memory cell groups of the arrangements , each arrangement containing at least one additional memory cell group (32, 33) which are categorized according to the Bus system and whose outputs are normally masked. 10. Electronic data processing text system according to claims 6 and 9, characterized in that each additional memory cell group (32, 33; Fig. 4) is connected to the common additional manifold (S). 11. Electronic data processing system according to one or more of claims 7 to 10, characterized in that that in each function storage unit a device is provided which is derived from the twin arrangement of the function storage unit selects only one arrangement for operation at a time. 209833/11