GB1316462A - Method and circuit arrangements for the rror-correction of information - Google Patents

Method and circuit arrangements for the rror-correction of information

Info

Publication number
GB1316462A
GB1316462A GB2738970A GB2738970A GB1316462A GB 1316462 A GB1316462 A GB 1316462A GB 2738970 A GB2738970 A GB 2738970A GB 2738970 A GB2738970 A GB 2738970A GB 1316462 A GB1316462 A GB 1316462A
Authority
GB
United Kingdom
Prior art keywords
error
groups
reinverted
inverter
inverted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2738970A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Licentia Patent Verwaltungs GmbH
Original Assignee
Licentia Patent Verwaltungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19691928673 external-priority patent/DE1928673C3/de
Priority claimed from DE2025340A external-priority patent/DE2025340B2/de
Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Publication of GB1316462A publication Critical patent/GB1316462A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
GB2738970A 1969-06-06 1970-06-05 Method and circuit arrangements for the rror-correction of information Expired GB1316462A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19691928673 DE1928673C3 (de) 1969-06-06 Verfahren und Schaltungsanordnungen zur Einfachfehlerkorrektur von Informationen
DE2025340A DE2025340B2 (de) 1970-05-23 1970-05-23 Verfahren und Schaltungsanordnungen zur Fehlerkorrektur von Informationen

Publications (1)

Publication Number Publication Date
GB1316462A true GB1316462A (en) 1973-05-09

Family

ID=25757457

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2738970A Expired GB1316462A (en) 1969-06-06 1970-06-05 Method and circuit arrangements for the rror-correction of information

Country Status (3)

Country Link
US (1) US3665393A (enExample)
FR (1) FR2050036A5 (enExample)
GB (1) GB1316462A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8699514B2 (en) 2007-01-12 2014-04-15 Broadcom Corporation Multi-rate MAC to PHY interface
US9330043B2 (en) 2002-10-29 2016-05-03 Broadcom Corporation Multi-rate, multi-port, gigabit SERDES transceiver

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3768071A (en) * 1972-01-24 1973-10-23 Ibm Compensation for defective storage positions
GB1535185A (en) * 1975-05-17 1978-12-13 Plessey Co Ltd Multiprocessor data processing system peripheral equipment access unit
US4037091A (en) * 1976-04-05 1977-07-19 Bell Telephone Laboratories, Incorporated Error correction circuit utilizing multiple parity bits
US4577059A (en) * 1982-01-29 1986-03-18 Gretag Aktiengesellschaft Decoding process and apparatus
AU4798793A (en) * 1992-08-10 1994-03-03 Monolithic System Technology, Inc. Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration
US8365044B2 (en) * 2007-04-23 2013-01-29 Agere Systems Inc. Memory device with error correction based on automatic logic inversion

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9330043B2 (en) 2002-10-29 2016-05-03 Broadcom Corporation Multi-rate, multi-port, gigabit SERDES transceiver
US8699514B2 (en) 2007-01-12 2014-04-15 Broadcom Corporation Multi-rate MAC to PHY interface
US9379988B2 (en) 2007-01-12 2016-06-28 Broadcom Corporation Multi-rate MAC to PHY interface

Also Published As

Publication number Publication date
FR2050036A5 (enExample) 1971-03-26
US3665393A (en) 1972-05-23

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee