GB1310219A - Data clocking system - Google Patents

Data clocking system

Info

Publication number
GB1310219A
GB1310219A GB1310219DA GB1310219A GB 1310219 A GB1310219 A GB 1310219A GB 1310219D A GB1310219D A GB 1310219DA GB 1310219 A GB1310219 A GB 1310219A
Authority
GB
United Kingdom
Prior art keywords
clocking
period
periods
store
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1310219A publication Critical patent/GB1310219A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

1310219 Digital transmission; synchronizing INTERNATIONAL BUSINESS MACHINES CORP 5 Oct 1971 46177/71 Heading H4P A synchronizing system comprises a stored table with a look up system from which successive locations are read to provide selection of a plurality of sampling periods within each clocking period. A number of locations are scanned during each clocking period so that such period is extended or reduced, temporarily, until approximate synchronization is attained. The number of locations read is smaller or greater dependent on whether the clocking periods are advanced or retarded with respect to input signals. The basic clock period is divided into 31 sampling periods. When transitions of the sampling periods are slow relative to the incoming signals, e.g. input transitions occur in any of sample periods 1-14 the clock period is increased by one sampling period to 32 by which is maintained until the input signal is approximately synchronized, when it reverts to 31. Conversely if the clocking signal is fast the clock period is shortened to one having 30 sample periods. In practice clock period alteration is delayed until a number, e.g. 3 slow or fast successive clocking signals are detected. The phase of clocking signals relative to input signals alters about 3% per cycle but this may be increased under starting conditions by forcing a number into a sample buffer included in sync. store (2), Fig. 2 (not shown). Input signals may be presented on a plurality of lines which may have differing speeds preferably multiples of each other hence adjustment may be made by the provision of divisors. The sync. store (2) performs also logical operations and generation of differing sampling periods. Such operations can be performed by an associative store of the type disclosed in Specification 1,218,406 using table look up techniques, initiation of operation being based on a comparison of the state of an input signal with its state at a prior time. Fig. 3 (not shown) illustrates a layout for the sync. store words occupying horizontal rows, each row being divided into tables.
GB1310219D 1971-10-05 1971-10-05 Data clocking system Expired GB1310219A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4617771 1971-10-05

Publications (1)

Publication Number Publication Date
GB1310219A true GB1310219A (en) 1973-03-14

Family

ID=10440179

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1310219D Expired GB1310219A (en) 1971-10-05 1971-10-05 Data clocking system

Country Status (4)

Country Link
JP (1) JPS4846255A (en)
DE (1) DE2247793A1 (en)
FR (1) FR2155546A5 (en)
GB (1) GB1310219A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108022A (en) * 1979-02-13 1980-08-19 Hitachi Ltd Data processor
JP2933219B2 (en) * 1987-08-19 1999-08-09 三菱化学株式会社 Correction method for signal out-of-sync

Also Published As

Publication number Publication date
DE2247793A1 (en) 1973-04-19
FR2155546A5 (en) 1973-05-18
JPS4846255A (en) 1973-07-02

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee