FR2155546A5 - - Google Patents

Info

Publication number
FR2155546A5
FR2155546A5 FR7235074A FR7235074A FR2155546A5 FR 2155546 A5 FR2155546 A5 FR 2155546A5 FR 7235074 A FR7235074 A FR 7235074A FR 7235074 A FR7235074 A FR 7235074A FR 2155546 A5 FR2155546 A5 FR 2155546A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7235074A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of FR2155546A5 publication Critical patent/FR2155546A5/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
FR7235074A 1971-10-05 1972-09-27 Expired FR2155546A5 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4617771 1971-10-05

Publications (1)

Publication Number Publication Date
FR2155546A5 true FR2155546A5 (fr) 1973-05-18

Family

ID=10440179

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7235074A Expired FR2155546A5 (fr) 1971-10-05 1972-09-27

Country Status (4)

Country Link
JP (1) JPS4846255A (fr)
DE (1) DE2247793A1 (fr)
FR (1) FR2155546A5 (fr)
GB (1) GB1310219A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108022A (en) * 1979-02-13 1980-08-19 Hitachi Ltd Data processor
JP2933219B2 (ja) * 1987-08-19 1999-08-09 三菱化学株式会社 信号の同期ずれ補正方法

Also Published As

Publication number Publication date
DE2247793A1 (de) 1973-04-19
JPS4846255A (fr) 1973-07-02
GB1310219A (en) 1973-03-14

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Legal Events

Date Code Title Description
ST Notification of lapse