GB1246022A - Method of manufacturing semiconductor devices - Google Patents

Method of manufacturing semiconductor devices

Info

Publication number
GB1246022A
GB1246022A GB4290669A GB4290669A GB1246022A GB 1246022 A GB1246022 A GB 1246022A GB 4290669 A GB4290669 A GB 4290669A GB 4290669 A GB4290669 A GB 4290669A GB 1246022 A GB1246022 A GB 1246022A
Authority
GB
United Kingdom
Prior art keywords
wafer
groove
type layer
etching
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4290669A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1246022A publication Critical patent/GB1246022A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting

Abstract

1,246,022. Semi-conductor devices. HITACHI Ltd. 28 Aug., 1969 [14 Sept., 1968], No. 42906/69. Heading H1K. A semi-conductor device having a bevelled peripheral surface is manufactured by scribing an endless groove 19 in a main surface of a wafer to produce a mechanically strained layer 20 adjacent to the groove encompassing a device formed in the wafer and then etching the groove mechanically to drive it into the wafer. The device described comprises a P+type layer separated from an N+type layer by an N-type layer, and the etching of the groove is continued until it extends at least through the N-type layer if not through the wafer, so that a peripheral surface at an angle to the PN junction 16 is formed around the device. The groove 19 is initially formed by scribing with a diamond cutter to a depth of 10-15 microns whilst the wafer is fixed to a support wafer 18 by Apiezon wax 17. During etching, surfaces not to be attacked by the etchant are protected by a wax layer.
GB4290669A 1968-09-14 1969-08-28 Method of manufacturing semiconductor devices Expired GB1246022A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6647168A JPS5026903B1 (en) 1968-09-14 1968-09-14

Publications (1)

Publication Number Publication Date
GB1246022A true GB1246022A (en) 1971-09-15

Family

ID=13316716

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4290669A Expired GB1246022A (en) 1968-09-14 1969-08-28 Method of manufacturing semiconductor devices

Country Status (2)

Country Link
JP (1) JPS5026903B1 (en)
GB (1) GB1246022A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2220877A1 (en) * 1973-03-09 1974-10-04 Thomson Csf PIN diodes collectively made from PIN chip - are formed between electrodes by etching parallel trenches in two stages followed by separation
US3961354A (en) * 1972-11-17 1976-06-01 Matsushita Electronics Corporation Mesa type thyristor and its making method
FR2363888A1 (en) * 1976-09-03 1978-03-31 Philips Nv PROCESS FOR THE REALIZATION OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THUS REALIZED
DE4204436A1 (en) * 1992-02-14 1993-08-19 Daimler Benz Ag Semiconductor device mfr. from thin foil - using semiconductor supports during foil growth and structuring operations
EP0566929A1 (en) * 1992-04-21 1993-10-27 ANT Nachrichtentechnik GmbH Method for manufacturing micromechanical structures from monocrystalline semi-conductor material

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961354A (en) * 1972-11-17 1976-06-01 Matsushita Electronics Corporation Mesa type thyristor and its making method
FR2220877A1 (en) * 1973-03-09 1974-10-04 Thomson Csf PIN diodes collectively made from PIN chip - are formed between electrodes by etching parallel trenches in two stages followed by separation
FR2363888A1 (en) * 1976-09-03 1978-03-31 Philips Nv PROCESS FOR THE REALIZATION OF A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THUS REALIZED
DE4204436A1 (en) * 1992-02-14 1993-08-19 Daimler Benz Ag Semiconductor device mfr. from thin foil - using semiconductor supports during foil growth and structuring operations
EP0566929A1 (en) * 1992-04-21 1993-10-27 ANT Nachrichtentechnik GmbH Method for manufacturing micromechanical structures from monocrystalline semi-conductor material

Also Published As

Publication number Publication date
JPS5026903B1 (en) 1975-09-04

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