GB1243865A - Means for the conversion of a decimal number in bcd form into a pure binary number - Google Patents
Means for the conversion of a decimal number in bcd form into a pure binary numberInfo
- Publication number
- GB1243865A GB1243865A GB4320769A GB4320769A GB1243865A GB 1243865 A GB1243865 A GB 1243865A GB 4320769 A GB4320769 A GB 4320769A GB 4320769 A GB4320769 A GB 4320769A GB 1243865 A GB1243865 A GB 1243865A
- Authority
- GB
- United Kingdom
- Prior art keywords
- binary
- except
- last
- decimal
- bcd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/12—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word having two radices, e.g. binary-coded-decimal code
Abstract
1,243,865. Decimal-to-binary converters. MESSERSCHMITT - BOLKOW - BLOHM G.m.b.H. 29 Aug.. 1969. [5 Sept.. 1968], No. 43207/69. Heading G4A. A BCD-to-pure-binary converter comprises a number of binary full adders, each (except the last) feeding sum and carry signals to the next, and each BCD input line (except the least significant) going to all the adder inputs associated with those powers of two which added together give the value of the input line. As disclosed, six 4-bit parallel binary adders are used for three decimal orders, each except the last feeding three sum bits and a carry bit to the next and providing one bit of the final binary output. The last adder provides four bits of the output.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19681774781 DE1774781A1 (en) | 1968-09-05 | 1968-09-05 | Circuit arrangement for converting a decimal number in the BCD code into a pure binary number |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1243865A true GB1243865A (en) | 1971-08-25 |
Family
ID=5702267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4320769A Expired GB1243865A (en) | 1968-09-05 | 1969-08-29 | Means for the conversion of a decimal number in bcd form into a pure binary number |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS5221096Y1 (en) |
DE (1) | DE1774781A1 (en) |
FR (1) | FR2017448A1 (en) |
GB (1) | GB1243865A (en) |
-
1968
- 1968-09-05 DE DE19681774781 patent/DE1774781A1/en active Pending
-
1969
- 1969-08-29 GB GB4320769A patent/GB1243865A/en not_active Expired
- 1969-09-04 FR FR6930216A patent/FR2017448A1/fr not_active Withdrawn
-
1976
- 1976-01-05 JP JP8276U patent/JPS5221096Y1/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE1774781A1 (en) | 1972-02-17 |
DE1774781B2 (en) | 1973-11-08 |
FR2017448A1 (en) | 1970-05-22 |
JPS5221096Y1 (en) | 1977-05-14 |
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