GB1214198A - A programmed apparatus for the serial handling of numerical information - Google Patents
A programmed apparatus for the serial handling of numerical informationInfo
- Publication number
- GB1214198A GB1214198A GB6078168A GB6078168A GB1214198A GB 1214198 A GB1214198 A GB 1214198A GB 6078168 A GB6078168 A GB 6078168A GB 6078168 A GB6078168 A GB 6078168A GB 1214198 A GB1214198 A GB 1214198A
- Authority
- GB
- United Kingdom
- Prior art keywords
- digit
- digits
- shift register
- word
- delay line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
- G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
1,214,198. Data processor. FRIDEN HOLLAND N.V. 20 Dec., 1968 [22 Dec., 1967], No. 60781/68. Heading G4A. Digital electric calculator has a delay line memory 2 connected in a closed loop with a calculator unit 1 containing an adder-subtractor 6 and a shift register 5, the delay line containing numerical words interlaced with corresponding digits of each word adjacent each other, the digits being composed of a predetermined fixed number of bits and the register having an equal number of stages. The delay line shown contains eight registers each holding a twelve-digit binary coded decimal number. The digits pass via an amplifier 3 to a series of switches in the calculator unit. To perform an addition or subtraction on adjacent digits the first digit to be operated on is fed to the shift register. When the first bit of the following digit leaves amplifier 3 it is fed to the adder-subtractor 6. At the same time the first bit of the earlier digit leaves the shift register to enter amplifier 4 and is also fed to the adder-subtractor. The addersubtractor output is at the same time connected to the shift register input so that the sum of the input bits is stored in the shift register. At the end of the arithmetic operation the switches are arranged to feed the data through the shift register. Any corrections required to produce appropriate carries are carried out on the next circulation when a 6 is added to or subtracted from the b.c.d. number via input d where necessary, any carries to the next digit being held in flip-flop 8. If two spaced digits are to be operated on, for instance the digits in the first and fifth registers, then the digit of the first word is passed by the shift register to enter the delay line but when the digit of the second word is in the delay line the remaining words are connected to pass via the unit 6 until the digit of the last word has passed, the second word digit meanwhile recirculating in the shift register and then the second word digit is added to the end of the group containing the corresponding digits. Thus the register digits are in the order 2.6.5.4.3.1. This is repeated until the required digits are adjacent.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL6717570A NL6717570A (en) | 1967-12-22 | 1967-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1214198A true GB1214198A (en) | 1970-12-02 |
Family
ID=19802075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB6078168A Expired GB1214198A (en) | 1967-12-22 | 1968-12-20 | A programmed apparatus for the serial handling of numerical information |
Country Status (5)
| Country | Link |
|---|---|
| DE (1) | DE1815817A1 (en) |
| ES (1) | ES361727A1 (en) |
| FR (1) | FR1603566A (en) |
| GB (1) | GB1214198A (en) |
| NL (1) | NL6717570A (en) |
-
1967
- 1967-12-22 NL NL6717570A patent/NL6717570A/xx unknown
-
1968
- 1968-12-19 FR FR1603566D patent/FR1603566A/fr not_active Expired
- 1968-12-19 DE DE19681815817 patent/DE1815817A1/en active Pending
- 1968-12-20 GB GB6078168A patent/GB1214198A/en not_active Expired
- 1968-12-20 ES ES361727A patent/ES361727A1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE1815817A1 (en) | 1969-08-28 |
| ES361727A1 (en) | 1970-09-16 |
| NL6717570A (en) | 1969-06-24 |
| FR1603566A (en) | 1971-05-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PLNP | Patent lapsed through nonpayment of renewal fees |