GB1176326A - Improvements in and relating to Semiconductor Devices - Google Patents

Improvements in and relating to Semiconductor Devices

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Publication number
GB1176326A
GB1176326A GB40804/66A GB4080466A GB1176326A GB 1176326 A GB1176326 A GB 1176326A GB 40804/66 A GB40804/66 A GB 40804/66A GB 4080466 A GB4080466 A GB 4080466A GB 1176326 A GB1176326 A GB 1176326A
Authority
GB
United Kingdom
Prior art keywords
metallization
level
metallized
lowest
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB40804/66A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1176326A publication Critical patent/GB1176326A/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Die Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1,176,326. Semi-conductor devices; semiconductor circuit assemblies. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 13 Sept., 1966 [24 March, 1966], No. 40804/66. Headings H1K and H1R. A semi-conductor device comprises an insulating substrate 1 (Fig. 1) with metallization at three levels 10, 16, 15. An active semiconductor device, e.g. the planar silicon transistor shown, is mounted on the metallization at the lowest (or the intermediate) level which is connected to metallization at the upper level to provide an external collector connection. The interdigitated emitter 21 and base 22 are connected to metallization at the intermediate (or lowest) level which extends on to the top level to provide external connections 13, 15. In the embodiment the substrate is of alumina, beryllia or boron nitride extruded and cut to the form shown, or of moulded glass. The contoured surface is metallized overall by sputtering with titanium and then vapour depositing first platinum and then gold, which is thickened by electroplating if desired. Alternatively, it is metallized by the molybdenum-manganese process. Slots 7 and 8 are next cut to isolate parts of the metallization, though this may be avoided if metallization if effected through a mask. After attaching the transistor by heating to 400‹ C. wires 25, 26 are thermocompression bonded to its electrodes and the metallized intermediate levels and then embedded in epoxy resin. The arrangement is such that the interconnections and resin lie wholly within the channel so that the device is protected against damage and can be bonded directly to contact channel so that the device is protected against damage and can be bonded directly to contact areas of a printed circuit in an inverted position (Fig. 3, not shown). One or more diodes or a tetrode may be mounted on modified substrates providing all the requisite external connections at the upper level.
GB40804/66A 1966-03-24 1967-03-13 Improvements in and relating to Semiconductor Devices Expired GB1176326A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US53705766A 1966-03-24 1966-03-24

Publications (1)

Publication Number Publication Date
GB1176326A true GB1176326A (en) 1970-01-01

Family

ID=24141009

Family Applications (1)

Application Number Title Priority Date Filing Date
GB40804/66A Expired GB1176326A (en) 1966-03-24 1967-03-13 Improvements in and relating to Semiconductor Devices

Country Status (2)

Country Link
DE (1) DE1564444C3 (en)
GB (1) GB1176326A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198886A (en) * 1990-01-23 1993-03-30 U.S. Philips Corp. Semiconductor device having a clamping support

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2903587C2 (en) * 1979-01-31 1983-03-24 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Process for the production of opto-electronic coupling components
DE3147790A1 (en) * 1981-12-03 1983-06-09 Brown, Boveri & Cie Ag, 6800 Mannheim Power module and method of producing it
JPS58154239A (en) * 1982-03-09 1983-09-13 Mitsubishi Electric Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198886A (en) * 1990-01-23 1993-03-30 U.S. Philips Corp. Semiconductor device having a clamping support

Also Published As

Publication number Publication date
DE1564444A1 (en) 1970-01-08
DE1564444C3 (en) 1978-05-11
DE1564444B2 (en) 1977-09-15

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