GB1040778A - High speed adder - Google Patents

High speed adder

Info

Publication number
GB1040778A
GB1040778A GB2507064A GB2507064A GB1040778A GB 1040778 A GB1040778 A GB 1040778A GB 2507064 A GB2507064 A GB 2507064A GB 2507064 A GB2507064 A GB 2507064A GB 1040778 A GB1040778 A GB 1040778A
Authority
GB
United Kingdom
Prior art keywords
circuit
eqeq
numbers
carry
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2507064A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1040778A publication Critical patent/GB1040778A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Error Detection And Correction (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

1,040,778. Parallel adders. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. June 17, 1964 [June 20, 1963], No. 25070/64. Heading G4A. To increase the speed of operation of an adder, the numbers to be added are dealt with in a plurality of sections and a provisonal sum is formed for each section with the assumption that the input carry from the previous section is zero. A modifying circuit then modifies the provisional sum according to the true value of the input carry. Fig. 1 shows diagrammatically one such section operating on six bit positions x1-x6, y1-y6 of the numbers x and y to be added. In circuit 1i the signals d# = x#y# (AND), and e# = x# # y# (EXCLUSIVE OR) are formed. From these signals provisional sums Z‹K are formed and these are applied to the modifying circuit 3i together with the input carry Ci and the signals e#. In this circuit the true sums Z# are formed. The circuit 4i forms the output carry Ci+1 and also terms Pi = dq # eqdq-1 # eqeq-1dq-2 # ... #eqeq-1... ep-1dp and Qi = eqeq-1 ... ep where the section extends from the pth to the qth positions of the numbers to be added. These terms are applied to circuit 5 to form the end-around carry for use in subtraction by ones complement addition. Fig. 3 (not shown) shows the logical circuitry used to perform the above operations. The equations which the circuitry represents are listed in Figs. 2a and 2b (not shown), and described in the Specification.
GB2507064A 1963-06-20 1964-06-17 High speed adder Expired GB1040778A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL294369 1963-06-20

Publications (1)

Publication Number Publication Date
GB1040778A true GB1040778A (en) 1966-09-01

Family

ID=19754800

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2507064A Expired GB1040778A (en) 1963-06-20 1964-06-17 High speed adder

Country Status (7)

Country Link
AT (1) AT248743B (en)
BE (1) BE649532A (en)
CH (1) CH424323A (en)
DE (1) DE1194606B (en)
GB (1) GB1040778A (en)
NL (1) NL294369A (en)
SE (1) SE306188B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171805A2 (en) * 1984-08-17 1986-02-19 Nec Corporation High speed digital arithmetic unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0171805A2 (en) * 1984-08-17 1986-02-19 Nec Corporation High speed digital arithmetic unit
EP0171805A3 (en) * 1984-08-17 1989-03-29 Nec Corporation High speed digital arithmetic unit

Also Published As

Publication number Publication date
DE1194606B (en) 1965-06-10
CH424323A (en) 1966-11-15
AT248743B (en) 1966-08-10
BE649532A (en) 1964-12-21
SE306188B (en) 1968-11-18
NL294369A (en)

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