GB1018614A - Improvements in or relating to magnetic logic "or" gates - Google Patents
Improvements in or relating to magnetic logic "or" gatesInfo
- Publication number
- GB1018614A GB1018614A GB1180561A GB1180561A GB1018614A GB 1018614 A GB1018614 A GB 1018614A GB 1180561 A GB1180561 A GB 1180561A GB 1180561 A GB1180561 A GB 1180561A GB 1018614 A GB1018614 A GB 1018614A
- Authority
- GB
- United Kingdom
- Prior art keywords
- core
- state
- output
- cores
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/80—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices
- H03K17/82—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices the devices being transfluxors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electronic Switches (AREA)
Abstract
1,018,614. Circuits employing bi-stable magnetic elements. PLESSEY CO. Ltd. June 29, 1962 [March 30, 1961], No. 11805/61. Heading H3B. A magnetic logical device includes two multiple aperture cores A 1 , A 2 which have their output windings 9A, 9A 2 connected in series with the input winding 7B of an output core B. The " OR " device of Fig. 6 has two inputs, one each to cores A 1 and A 2 , an input setting the core from the " 0 " state (Fig. 2A) to the " 1 " state (Fig. 2B). A primary pulse is then applied to A 1 and A 2 followed by a clearing pulse which causes core B to switch if either or both cores were set to the " 1 " state. The " primed 1 " state is shown in Fig. 2C. In the embodiment of Fig. 7 an N-input " OR " device has two output apertures in each core to cancel out the spurious outputs produced by a clearing pulse passing through a core in the " 0 " state (Fig. 1). The number of turns on an output winding is greater than that on an input winding to compensate for losses in the system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1180561A GB1018614A (en) | 1961-03-30 | 1961-03-30 | Improvements in or relating to magnetic logic "or" gates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1180561A GB1018614A (en) | 1961-03-30 | 1961-03-30 | Improvements in or relating to magnetic logic "or" gates |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1018614A true GB1018614A (en) | 1966-01-26 |
Family
ID=9993023
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1180561A Expired GB1018614A (en) | 1961-03-30 | 1961-03-30 | Improvements in or relating to magnetic logic "or" gates |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1018614A (en) |
-
1961
- 1961-03-30 GB GB1180561A patent/GB1018614A/en not_active Expired
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