GB1005197A - Data processing system - Google Patents

Data processing system

Info

Publication number
GB1005197A
GB1005197A GB3080362A GB3080362A GB1005197A GB 1005197 A GB1005197 A GB 1005197A GB 3080362 A GB3080362 A GB 3080362A GB 3080362 A GB3080362 A GB 3080362A GB 1005197 A GB1005197 A GB 1005197A
Authority
GB
United Kingdom
Prior art keywords
circuit
output
circuits
carry
majority logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3080362A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of GB1005197A publication Critical patent/GB1005197A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/388—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using other various devices such as electro-chemical, microwave, surface acoustic wave, neuristor, electron beam switching, resonant, e.g. parametric, ferro-resonant
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/19—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using non-linear reactive devices in resonant circuits
    • G11C11/20—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using non-linear reactive devices in resonant circuits using parametrons
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
    • H03K19/162—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices using parametrons
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4818—Threshold devices
    • G06F2207/4822—Majority gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
GB3080362A 1961-08-14 1962-08-10 Data processing system Expired GB1005197A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13128161A 1961-08-14 1961-08-14

Publications (1)

Publication Number Publication Date
GB1005197A true GB1005197A (en) 1965-09-22

Family

ID=22448732

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3080362A Expired GB1005197A (en) 1961-08-14 1962-08-10 Data processing system

Country Status (5)

Country Link
CH (1) CH418690A (de)
DE (1) DE1211006B (de)
FR (1) FR1337495A (de)
GB (1) GB1005197A (de)
NL (1) NL281599A (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0111055A2 (de) * 1982-11-30 1984-06-20 International Business Machines Corporation Kippschaltung mit differentieller Kaskodenstromschalterlogik
EP0295001A2 (de) * 1987-06-08 1988-12-14 AT&T Corp. Anordnung für CMOS-integrierten Schaltungsaufbau eines logischen Baumes mit Eingangsbelastbarkeit
WO2000017802A2 (en) * 1998-09-21 2000-03-30 Rn2R, L.L.C. Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0111055A2 (de) * 1982-11-30 1984-06-20 International Business Machines Corporation Kippschaltung mit differentieller Kaskodenstromschalterlogik
EP0111055A3 (en) * 1982-11-30 1986-12-30 International Business Machines Corporation Latch circuit with differential cascode current switch logic
EP0295001A2 (de) * 1987-06-08 1988-12-14 AT&T Corp. Anordnung für CMOS-integrierten Schaltungsaufbau eines logischen Baumes mit Eingangsbelastbarkeit
EP0295001A3 (en) * 1987-06-08 1989-04-26 American Telephone And Telegraph Company Cmos integrated circuit fan-in logic tree layout arrangement
WO2000017802A2 (en) * 1998-09-21 2000-03-30 Rn2R, L.L.C. Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
WO2000017802A3 (en) * 1998-09-21 2000-07-20 Rn2R L L C Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
US6205458B1 (en) 1998-09-21 2001-03-20 Rn2R, L.L.C. Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith

Also Published As

Publication number Publication date
FR1337495A (fr) 1963-09-13
NL281599A (de) 1964-12-10
CH418690A (de) 1966-08-15
DE1211006B (de) 1966-02-17

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