NL281599A - - Google Patents

Info

Publication number
NL281599A
NL281599A NL281599DA NL281599A NL 281599 A NL281599 A NL 281599A NL 281599D A NL281599D A NL 281599DA NL 281599 A NL281599 A NL 281599A
Authority
NL
Netherlands
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of NL281599A publication Critical patent/NL281599A/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02Comparing digital values
    • G06F7/026Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/388Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using other various devices such as electro-chemical, microwave, surface acoustic wave, neuristor, electron beam switching, resonant, e.g. parametric, ferro-resonant
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/19Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using non-linear reactive devices in resonant circuits
    • G11C11/20Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using non-linear reactive devices in resonant circuits using parametrons
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00323Delay compensation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
    • H03K19/162Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices using parametrons
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731Optimisation thereof
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802Special implementations
    • G06F2207/4818Threshold devices
    • G06F2207/4822Majority gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
NL281599D 1961-08-14 1962-07-31 NL281599A (xx)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13128161A 1961-08-14 1961-08-14

Publications (1)

Publication Number Publication Date
NL281599A true NL281599A (xx) 1964-12-10

Family

ID=22448732

Family Applications (1)

Application Number Title Priority Date Filing Date
NL281599D NL281599A (xx) 1961-08-14 1962-07-31

Country Status (5)

Country Link
CH (1) CH418690A (xx)
DE (1) DE1211006B (xx)
FR (1) FR1337495A (xx)
GB (1) GB1005197A (xx)
NL (1) NL281599A (xx)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4513283A (en) * 1982-11-30 1985-04-23 International Business Machines Corporation Latch circuits with differential cascode current switch logic
US4849751A (en) * 1987-06-08 1989-07-18 American Telephone And Telegraph Company, At&T Bell Laboratories CMOS Integrated circuit digital crossbar switching arrangement
US6205458B1 (en) 1998-09-21 2001-03-20 Rn2R, L.L.C. Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith

Also Published As

Publication number Publication date
DE1211006B (de) 1966-02-17
FR1337495A (fr) 1963-09-13
CH418690A (de) 1966-08-15
GB1005197A (en) 1965-09-22

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