FR1337495A - Système de traitement de l'information - Google Patents
Système de traitement de l'informationInfo
- Publication number
- FR1337495A FR1337495A FR906308A FR906308A FR1337495A FR 1337495 A FR1337495 A FR 1337495A FR 906308 A FR906308 A FR 906308A FR 906308 A FR906308 A FR 906308A FR 1337495 A FR1337495 A FR 1337495A
- Authority
- FR
- France
- Prior art keywords
- information processing
- processing system
- information
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/388—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using other various devices such as electro-chemical, microwave, surface acoustic wave, neuristor, electron beam switching, resonant, e.g. parametric, ferro-resonant
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/19—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using non-linear reactive devices in resonant circuits
- G11C11/20—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using non-linear reactive devices in resonant circuits using parametrons
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
- H03K19/162—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices using parametrons
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
- G06F2207/4818—Threshold devices
- G06F2207/4822—Majority gates
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13128161A | 1961-08-14 | 1961-08-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
FR1337495A true FR1337495A (fr) | 1963-09-13 |
Family
ID=22448732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR906308A Expired FR1337495A (fr) | 1961-08-14 | 1962-08-07 | Système de traitement de l'information |
Country Status (5)
Country | Link |
---|---|
CH (1) | CH418690A (de) |
DE (1) | DE1211006B (de) |
FR (1) | FR1337495A (de) |
GB (1) | GB1005197A (de) |
NL (1) | NL281599A (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4513283A (en) * | 1982-11-30 | 1985-04-23 | International Business Machines Corporation | Latch circuits with differential cascode current switch logic |
US4849751A (en) * | 1987-06-08 | 1989-07-18 | American Telephone And Telegraph Company, At&T Bell Laboratories | CMOS Integrated circuit digital crossbar switching arrangement |
US6205458B1 (en) * | 1998-09-21 | 2001-03-20 | Rn2R, L.L.C. | Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith |
-
1962
- 1962-07-14 DE DES80409A patent/DE1211006B/de active Pending
- 1962-07-31 NL NL281599D patent/NL281599A/xx unknown
- 1962-08-02 CH CH926562A patent/CH418690A/de unknown
- 1962-08-07 FR FR906308A patent/FR1337495A/fr not_active Expired
- 1962-08-10 GB GB3080362A patent/GB1005197A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
NL281599A (de) | 1964-12-10 |
GB1005197A (en) | 1965-09-22 |
CH418690A (de) | 1966-08-15 |
DE1211006B (de) | 1966-02-17 |
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