FR3118268B1 - Mémoire sécurisée - Google Patents

Mémoire sécurisée Download PDF

Info

Publication number
FR3118268B1
FR3118268B1 FR2014086A FR2014086A FR3118268B1 FR 3118268 B1 FR3118268 B1 FR 3118268B1 FR 2014086 A FR2014086 A FR 2014086A FR 2014086 A FR2014086 A FR 2014086A FR 3118268 B1 FR3118268 B1 FR 3118268B1
Authority
FR
France
Prior art keywords
column
binary data
bit
memory cells
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2014086A
Other languages
English (en)
Other versions
FR3118268A1 (fr
Inventor
Drissi Faress Tissafi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics France SAS
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR2014086A priority Critical patent/FR3118268B1/fr
Priority to US17/556,039 priority patent/US11978530B2/en
Priority to CN202111590551.4A priority patent/CN114664341A/zh
Publication of FR3118268A1 publication Critical patent/FR3118268A1/fr
Application granted granted Critical
Publication of FR3118268B1 publication Critical patent/FR3118268B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Storage Device Security (AREA)

Abstract

Mémoire sécurisée La présente description concerne une mémoire (40) comprenant des cellules mémoire (14) agencées en rangées et en colonnes, au moins une ligne de bits (20, 22), pour chaque colonne, reliée aux cellules mémoire de la colonne, et un circuit de lecture/écriture (24), reliés aux lignes de bits, configuré pour recevoir, pour chaque colonne, une donnée binaire (Di) à mémoriser dans l'une des cellules mémoire de la colonne, le circuit de lecture/écriture comprenant, pour chaque colonne, un verrou (46) configuré pour stocker un bit d'une clé, et un circuit de cryptage configuré pour crypter la donnée binaire reçue avec le bit de la clé pour fournir une donnée binaire crypté, le circuit de lecture/écriture étant configuré pour commander la ligne de bits pour mémoriser la donnée binaire cryptée. Figure pour l'abrégé : Fig. 4
FR2014086A 2020-12-23 2020-12-23 Mémoire sécurisée Active FR3118268B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2014086A FR3118268B1 (fr) 2020-12-23 2020-12-23 Mémoire sécurisée
US17/556,039 US11978530B2 (en) 2020-12-23 2021-12-20 Secure memory
CN202111590551.4A CN114664341A (zh) 2020-12-23 2021-12-23 安全存储器

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2014086 2020-12-23
FR2014086A FR3118268B1 (fr) 2020-12-23 2020-12-23 Mémoire sécurisée

Publications (2)

Publication Number Publication Date
FR3118268A1 FR3118268A1 (fr) 2022-06-24
FR3118268B1 true FR3118268B1 (fr) 2024-01-12

Family

ID=76034674

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2014086A Active FR3118268B1 (fr) 2020-12-23 2020-12-23 Mémoire sécurisée

Country Status (3)

Country Link
US (1) US11978530B2 (fr)
CN (1) CN114664341A (fr)
FR (1) FR3118268B1 (fr)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100201396B1 (ko) * 1996-07-20 1999-06-15 구본준 이피롬의 비화코드 해독 방지회로
DE10121837C1 (de) * 2001-05-04 2002-12-05 Infineon Technologies Ag Speicherschaltung mit mehreren Speicherbereichen
US6996692B2 (en) * 2002-04-17 2006-02-07 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for providing security for the same
KR20140020057A (ko) * 2012-08-07 2014-02-18 삼성전자주식회사 키 제어 로직을 포함하는 플래시 메모리 장치 및 그것의 암호화 키 저장 방법
US9116796B2 (en) * 2012-11-09 2015-08-25 Sandisk Technologies Inc. Key-value addressed storage drive using NAND flash based content addressable memory
JP7109992B2 (ja) * 2018-05-22 2022-08-01 キオクシア株式会社 メモリシステムおよび制御方法
KR102124064B1 (ko) * 2018-07-17 2020-06-17 한국과학기술연구원 플래시 메모리 시스템 및 그것의 양자화 신호 생성 방법
US11514174B2 (en) * 2019-01-23 2022-11-29 Micron Technology, Inc. Memory devices with cryptographic components
US11081168B2 (en) * 2019-05-23 2021-08-03 Hefei Reliance Memory Limited Mixed digital-analog memory devices and circuits for secure storage and computing
DE112019007421T5 (de) * 2019-05-31 2022-02-24 Micron Technology, Inc. Speichergerät mit sicherer testmoduseingabe

Also Published As

Publication number Publication date
CN114664341A (zh) 2022-06-24
US20220199133A1 (en) 2022-06-23
US11978530B2 (en) 2024-05-07
FR3118268A1 (fr) 2022-06-24

Similar Documents

Publication Publication Date Title
US20030105967A1 (en) Apparatus for encrypting data and method thereof
FR3088767B1 (fr) Circuit memoire adapte a mettre en oeuvre des operations de calcul
US20200310989A1 (en) Method and apparatus to generate zero content over garbage data when encryption parameters are changed
GB2004394B (en) Portable data carrier provided with a microprocessor and a programmable read-only memory
KR940004820A (ko) 반도체 메모리 장치
TW384539B (en) Semiconductor memory device having copy dsta protect function and method for accessing the same
EP2899639B1 (fr) Mémoire non volatile et dispositif électronique
FR3118268B1 (fr) Mémoire sécurisée
CN102197435B (zh) 并行联想存储器
JP2003263892A5 (fr)
KR960004734B1 (ko) 정보 보호방법 및 정보기억미디어
US20040250104A1 (en) Method of processing data and data processing apparatus
JPS5986348A (ja) デ−タ暗号秘密保持用集積回路素子
TWI266333B (en) Method for writing data bits to a memory array
US20150149790A1 (en) Nonvolatile memory and electronic device
US10565055B2 (en) Semiconductor memory device including an error correction code circuit
Pan et al. A MLC STT-MRAM based computing in-memory architec-ture for binary neural network
GB2603371A (en) Crypto-erasure via internal and/or external action
TWI541806B (zh) 內容可定址記憶體
US10373528B2 (en) Cell-level realization of burn after reading for NAND flash
JPH01107398A (ja) 半導体記憶装置
US5973986A (en) Memory device including a column decoder for decoding five columns
CN116167104A (zh) 三态内容寻址存储器的加扰装置、加扰方法及芯片
JP2002269909A (ja) 記録媒体ドライブの保安装置及び方法
KR960003846B1 (ko) 전송로에 의해 원격적 또는 국부적으로 연결된 송,수신장치사이의 데이터 전송을 확실히 식별하는 방법

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20220624

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

CA Change of address

Effective date: 20240708

CD Change of name or company name

Owner name: STMICROELECTRONICS FRANCE, FR

Effective date: 20240708

CJ Change in legal form

Effective date: 20240708