FR3110261B1 - METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT - Google Patents

METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT Download PDF

Info

Publication number
FR3110261B1
FR3110261B1 FR2004947A FR2004947A FR3110261B1 FR 3110261 B1 FR3110261 B1 FR 3110261B1 FR 2004947 A FR2004947 A FR 2004947A FR 2004947 A FR2004947 A FR 2004947A FR 3110261 B1 FR3110261 B1 FR 3110261B1
Authority
FR
France
Prior art keywords
integrated circuit
rewritable memory
testing
logic
flops
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2004947A
Other languages
French (fr)
Other versions
FR3110261A1 (en
Inventor
Samuel Charbouillot
Anthony Maure
Jean-Pascal Maraninchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idemia Starchip SAS
Original Assignee
Idemia Starchip SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Idemia Starchip SAS filed Critical Idemia Starchip SAS
Priority to FR2004947A priority Critical patent/FR3110261B1/en
Priority to TW110117474A priority patent/TWI797622B/en
Priority to CN202110529993.1A priority patent/CN113687208A/en
Publication of FR3110261A1 publication Critical patent/FR3110261A1/en
Application granted granted Critical
Publication of FR3110261B1 publication Critical patent/FR3110261B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1802—Address decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/003—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation in serial memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L’invention concerne un procédé et un système de test d’un circuit intégré comportant des portes logiques, des bascules logiques et une mémoire réinscriptible, le circuit intégré comportant une horloge interne, le circuit intégré étant configurable dans un mode de fonctionnement dit mode chaîne de balayage. Selon l’invention : - on met le circuit intégré dans le mode chaîne de balayage, - on isole avec des moyens d’isolement la mémoire réinscriptible des portes logiques des bascules logiques, - on cadence (Clk) les moyens d’isolement par une horloge externe, - on varie la périodicité de l’horloge externe, - on lit (300) le contenu de la mémoire réinscriptible et on le compare à une valeur, - on détermine (300) le temps d’accès de la mémoire réinscriptible en fonction de la comparaison. Fig. 3The invention relates to a method and a system for testing an integrated circuit comprising logic gates, logic flip-flops and a rewritable memory, the integrated circuit comprising an internal clock, the integrated circuit being configurable in an operating mode called chain mode sweep. According to the invention: - the integrated circuit is placed in scan chain mode, - the rewritable memory of the logic gates of the logic flip-flops is isolated with isolation means, - the isolation means are clocked (Clk) by a external clock, - the periodicity of the external clock is varied, - the content of the rewritable memory is read (300) and it is compared with a value, - the access time of the rewritable memory is determined (300) by comparison function. Fig. 3

FR2004947A 2020-05-18 2020-05-18 METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT Active FR3110261B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2004947A FR3110261B1 (en) 2020-05-18 2020-05-18 METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT
TW110117474A TWI797622B (en) 2020-05-18 2021-05-14 Method and system for testing an integrated circuit
CN202110529993.1A CN113687208A (en) 2020-05-18 2021-05-14 Method and system for testing integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2004947A FR3110261B1 (en) 2020-05-18 2020-05-18 METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT
FR2004947 2020-05-18

Publications (2)

Publication Number Publication Date
FR3110261A1 FR3110261A1 (en) 2021-11-19
FR3110261B1 true FR3110261B1 (en) 2022-04-29

Family

ID=72560696

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2004947A Active FR3110261B1 (en) 2020-05-18 2020-05-18 METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT

Country Status (3)

Country Link
CN (1) CN113687208A (en)
FR (1) FR3110261B1 (en)
TW (1) TWI797622B (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4878209A (en) * 1988-03-17 1989-10-31 International Business Machines Corporation Macro performance test
JP2003100100A (en) * 2001-07-19 2003-04-04 Mitsubishi Electric Corp Semiconductor integrated circuit device
US7103814B2 (en) * 2002-10-25 2006-09-05 International Business Machines Corporation Testing logic and embedded memory in parallel
DE602004007349T2 (en) * 2004-01-15 2008-03-13 Infineon Technologies Ag Device for determining the access time and / or the minimum cycle time of a memory
JP4707053B2 (en) * 2005-06-06 2011-06-22 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit device
TWI609190B (en) * 2016-08-05 2017-12-21 國立成功大學 Automatic-test architecture of integrated circuit capable of storing test data in scan chains and method thereof

Also Published As

Publication number Publication date
TW202147112A (en) 2021-12-16
TWI797622B (en) 2023-04-01
CN113687208A (en) 2021-11-23
FR3110261A1 (en) 2021-11-19

Similar Documents

Publication Publication Date Title
US7099783B2 (en) Semiconductor integrated circuit, design support apparatus, and test method
US7961559B2 (en) Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle
KR900007548B1 (en) Pattern masking method and an apparatus therefor
US20030149925A1 (en) Method and apparatus for implementing enhanced LBIST diagnostics of intermittent failures
US6496022B1 (en) Method and apparatus for reverse engineering integrated circuits by monitoring optical emission
US20120278672A1 (en) Architecture, system, method, and computer-accessible medium for toggle-based masking
KR101891362B1 (en) Fault detection system, extraction device, fault detection method, program, and recording medium
TWI398645B (en) Methods of locally in-order strobing,methods of jitter measurement and automated test equipment systems
US20080111558A1 (en) Defect localization based on defective cell diagnosis
Miceli et al. A laboratory score in the diagnosis of autoimmune atrophic gastritis: a prospective study
JP6654456B2 (en) Test point circuit, scan flip-flop for sequential test, semiconductor device and design device
FR3110261B1 (en) METHOD AND SYSTEM FOR TESTING AN INTEGRATED CIRCUIT
US10247777B1 (en) Detecting and locating shoot-through timing failures in a semiconductor integrated circuit
Holst et al. Variation-aware small delay fault diagnosis on compressed test responses
van Beek et al. Typical rise and fall of troponin in (peri-procedural) myocardial infarction: a systematic review
JP2013036903A (en) Fault spot estimation system, fault spot estimation method and program for fault spot estimation
US10078114B2 (en) Test point circuit, scan flip-flop for sequential test, semiconductor device and design device
US7750665B2 (en) Semiconductor device
US11005458B2 (en) Semiconductor integrated circuit adapted to scan testing, and method of designing the same
US7454674B2 (en) Digital jitter detector
KR20130039346A (en) Test apparatus for generating reference scan chain test data and test system
US8937494B1 (en) Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit
CN113609804B (en) Case generation method and device, test method and testability design method
US20020085439A1 (en) Method for reading semiconductor die information in a parallel test and burn-in system
Konopka et al. Clinical utility of quantitative multi-antibody Polycheck immunoassays in the diagnosis of coeliac disease

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20211119

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5