FR3107407A1 - Multilevel resonant cell inverter - Google Patents

Abstract

Multilevel inverter, comprising a set of capacitors (C) having a plurality of connection points and a set of switches (S1 to S6) arranged and connected to a control unit (UC) to successively connect each of the connection points with a first output line thus subjected to an AC output voltage. The set of switches comprises two parallel branches on which are respectively mounted a first inductor (L1) and a second inductor (L2) and between which are connected a first capacitor (C1) and a second capacitor (C2) to form a cell resonant subject to the alternating output voltage, the first capacitor and the second capacitor being connected to the branches in a crossed manner on either side of the inductors. FIGURE OF THE ABRIDGE: Fig. 3

Description

Resonant Cell Multilevel Inverter

BACKGROUND OF THE INVENTION

The present invention relates to the field of electrical energy conversion and more particularly electrical power converters such as inverters.

Inverters are typically used to supply electrical equipment, such as an electric motor, with alternating current/voltage from a direct current/voltage source.

An inverter is an electrical circuit arranged to output a sine wave having predetermined characteristics of amplitude, frequency and harmonic content. The wave must be as sinusoidal as possible. Indeed, the imperfections of the sinusoidal voltage generate a distortion of the harmonic current. This distortion increases the losses and causes significant heating of the motor.

There are many inverter topologies, each resulting in a trade-off between complexity and performance.

Among these topologies, we can distinguish controlled switching inverters which have a particular arrangement of switches which are controlled to provide a sine wave of variable amplitude and frequency.

An example of a voltage source controlled switching inverter is represented in figure 1, namely a multilevel inverter and more particularly here at three levels ANPC. This inverter comprises a first branch and a second branch connected in parallel to a positive connection point +DC and a negative connection point -DC. The first branch comprises two capacitors C connected in series at the positive connection point +DC and at the negative connection point –DC. The second branch comprises in series a first pair of transistors S1, S2 and a second pair of transistors S4, S6, the transistor S1 being connected to the positive connection point +DC and the transistor S6 being connected to the negative connection point -DC. A third branch is connected to the midpoint of the first pair of transistors S1, S2 and a fourth branch is connected to the midpoint of the second pair of transistors S4, S6. The third branch and the fourth branch respectively comprise a fifth transistor S3 and a sixth transistor S5 and are both connected to a first output line having an inductance Lf. A second output line is connected to the midpoint of the second branch (between the two pairs of transistors) and to the midpoint of the first branch (between the two capacitors C1, C2) to define with the first output line a voltage of output Vout. Transistors S1 to S6 are driven by a control circuit, not shown, according to a predetermined modulation law. An example of transistor modulation law is shown in Figure 2 which shows that:

• output voltage Vout is positive when transistor S1 is driven by a square wave signal, transistors S2 and S5 are driven by a square wave signal in phase opposition with the previous one, transistors S3 and S4 are on, transistor S6 is off ;
• output voltage Vout is negative when transistor S6 is driven by a square wave signal, transistors S3 and S4 are driven by a square wave signal in phase opposition with the previous one, transistors S2 and S5 are on, transistor S1 is off .

Square wave signals are usually operated as a series of pulses whose width is modulated to define the amplitude and frequency of the output voltage.

Controlled switching inverters have two main drawbacks, namely: switching losses on the one hand and strong voltage fronts (dV/dt) at the output generating electromagnetic disturbances on the other hand. These drawbacks are all the more troublesome the higher the frequency desired at the output.

In addition, in three-level inverters, the transistors are subjected to twice the voltage stress of that present in other inverter topologies.

OBJECT OF THE INVENTION

The aim of the invention is in particular to improve the performance of inverters with controlled switching.

To this end, provision is made, according to the invention, for a multilevel inverter, comprising a set of capacitors having a plurality of connection points and a set of switches arranged and connected to a control unit for successively connecting each of the connection points with a first output line thus subjected to an alternating output voltage. The set of switches comprises two parallel branches on which are respectively mounted a first inductor and a second inductor and between which are connected a first capacitor and a second capacitor to form a resonant cell subjected to the alternating output voltage, the first capacitor and the second capacitor being connected to the branches in a crossed manner on either side of the inductors.

Thus, the resonant cell forms a Z filter capable of absorbing all or part of the voltage fronts so that the inverter does not generate electromagnetic disturbances downstream.

Preferably, the inverter is a three-level inverter in which: the first inductor is mounted on the third branch, the second inductor is mounted on the fourth branch, the first capacitor is connected to a first terminal of the first inductor on the side of the first pair of transistors and to a second terminal of the second inductor on the side of the second assembly of transistors, and the second capacitor is connected to a first terminal of the second inductor on the side of the second pair of transistors and to a second terminal of the first inductor on the side of the first transistor assembly.

With this topology, the inverter allows soft switching, i.e. at 0V, while eliminating voltage edges on the output line.

Advantageously, the inverter comprises a fifth branch in parallel with the third branch and a sixth branch in parallel with the fourth branch, the fifth branch comprising a third inductor and a third assembly of transistors and the sixth branch comprising a fourth inductor and a fourth assembly of transistors.

This makes it possible to double the inductance value seen by the resonant current and therefore to play on the resonant frequency of the resonant cell.

Preferably, the control unit is arranged to drive the transistors as follows:

• the first transistor is driven by a square wave signal, the second transistor is driven by a square wave signal in phase opposition with the previous one, the first transistor assembly and the third transistor are conducting, the second transistor assembly and the fourth transistor are blocking so that the output voltage is positive;
• the fourth transistor is controlled by a square signal, the first assembly of transistors and the third transistor are controlled by a square signal in phase opposition with the previous one, the second transistor and the second assembly of transistors are on, the first transistor and the first assembly of transistors are blocking so that the output voltage is negative.

This control mode is used to suppress large voltage variations in the inverter.

Other characteristics and advantages of the invention will become apparent on reading the following description of a particular and non-limiting embodiment of the invention.

Reference will be made to the attached drawings, among which:

FIG. 1 is a diagram of a prior art three-level inverter;

FIG. 2 is a diagram illustrating the control law of this prior art three-level inverter;

FIG. 3 is a diagram of a three-level inverter according to the invention;

FIG. 4 is a diagram illustrating the control law of the inverter according to the invention;

FIG. 5 is a diagram of a three-level inverter according to a variant of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention is an inverter that can be used to control any actuator such as a motor having one or more phases. The connection of the inverter to the actuator and the adaptation of the inverter to the actuator (number of phases in particular) are known in themselves and will not be described here.

Referring to Figure 3, the inverter according to the invention comprises a first branch and a second branch connected in parallel to a positive connection point +DC and a negative connection point -DC.

The first branch comprises two capacitors C connected in series at the positive connection point +DC and at the negative connection point –DC.

The second branch comprises in series a first pair of transistors S1, S2 and a second pair of transistors S4, S6. The transistors S1, S2, S4, S6 are here MOSFET type field effect transistors (we note that it would be possible to use transistors of different type: IGBT, HEMT, etc.). The first transistor S1 has a drain connected to the positive terminal +DC and a source connected to the drain of the second transistor S2 whose source is connected to the drain of the third transistor S4. The source of the third transistor S4 is connected to the drain of the fourth transistor S6 which has a source connected to the negative terminal -DC. The second branch has a midpoint (between the two pairs of transistors) which is connected to a midpoint of the first branch (between the capacitors C) which forms a third connection point.

The inverter comprises a third branch connected to the midpoint of the first pair of transistors S1, S2 and a fourth branch connected to the midpoint of the second pair of transistors S4, S6. The third branch and the fourth branch respectively comprise a first assembly of transistors S3 comprising two transistors connected to a common drain, and a second assembly of transistors S5 comprising two transistors connected to a common drain. The third branch and the fourth branch are both connected to a first output line. The transistors of the first assembly of transistors S3 and of the second assembly of transistors S5 are here MOSFET type field effect transistors.

The inverter comprises a second output line connected to the midpoint of the first branch to define with the first output line an output voltage Vout.

The inverter comprises a resonant cell mounted in the set of switches to be subjected to an alternating voltage.

The resonant cell comprises a first inductor L1 mounted on the third branch and a second inductor L2 mounted on the fourth branch. The inductances L1 and L2 have the same value corresponding to the global inductance of the resonant cell. A first capacitor C1 is connected to a first terminal of the first inductor L1 on the side of the first pair of transistors S1, S2 and to a second terminal of the second inductor L2 on the side of the second assembly of transistors S5. A second capacitor C2 is connected to a first terminal of the second inductor L2 on the side of the second pair of transistors S4, S6 and to a second terminal of the first inductor L1 on the side of the first assembly of transistors S3. The capacitors C1, C2 are thus connected to the third branch and to the fourth branch in a crossed manner on either side of the inductors L1, L2 to form with the inductors L1, L2 a resonant circuit of the “Z source” type. Capacitors C1 and C2 have the same value corresponding to the overall capacitance of the resonant cell.

The control unit UC is arranged to drive the transistors S1 to S6 as follows (see figure 4):

• the first transistor S1 is driven by a square wave signal at a chopping frequency, the second transistor S2 is driven by a square wave signal in phase opposition with the previous one, the first assembly of transistors S3 and the third transistor S4 are on, the second assembly of transistors S5 and the fourth transistor S6 are blocking so that the output voltage Vout is positive;
• the fourth transistor S6 is driven by a square wave signal at the chopping frequency, the first assembly of transistors S3 and the third transistor S4 are driven by a square wave signal in phase opposition with the previous one, the second transistor S2 and the second assembly of transistors S5 are on, the first transistor S1 and the first assembly of transistors S3 are off so that the output voltage Vout is negative.

This driving mode allows smooth switching of the transistors.

The inverter device is in practice connected to a DC voltage source or to a rectifier bridge in such a way that the capacitors C are always supplied.

It is understood that the transistors S1 to S6 form a group of switches arranged and controlled to successively connect each of the connection points with the first output line which is thus subjected to an AC output voltage. The AC output voltage has characteristics depending on the chopping frequency.

The resonant frequency of the resonant cell and the selectivity of the Z filter formed by the resonant cell depend on the switching frequency. The shape of the output voltage is all the more sinusoidal as the resonant frequency is close to the chopping frequency. In addition, the gain is also greater in this case. On the other hand, the chopping frequency must be higher than the resonance frequency to benefit from switching at zero volts. The values of the inductors L1 and L2 and the value of the capacitors C1 and C2 are therefore chosen so that the resonant frequency is lower than the chopping frequency and to minimize the average value of the resonant current and maximize the interval of the duty cycle in switching at zero voltage.

The invention has several significant advantages:

• it allows the control of much faster motors (speed between 0 and 50.10e3 rad/s),
• it allows an increase in frequency without increasing the volume of the electronics (gain on cooling, on filters and decoupling capacities),
• it makes it possible to separate the power electronics and the motor, allowing a relaxation of the environmental constraints of the electronics,
• it allows the transmission of data on the power lines downstream of the inverter,
• it limits or even eliminates motor aging problems (insulation) caused by partial discharges,
• it limits or even eliminates the problems of electromagnetic radiation downstream of the inverter, and therefore the use of shielding to the detriment of mass and cost.

In the variant of Figure 5, the inverter comprises a fifth branch in parallel with the third branch and a sixth branch in parallel with the fourth branch. The fifth branch includes a third inductance L3 and a third assembly of transistors S7 and the sixth branch includes a fourth inductance L4 and a fourth assembly of transistors S8. The transistors of the third assembly of transistors S7 and of the fourth assembly of transistors S8 are statically controlled by the control unit UC. The third assembly of transistors S7 and the fourth assembly of transistors S8 are on and off at the same time as the first assembly of transistors S3 and the second assembly of transistors S5 if the conditions are satisfied at the command level.

Of course, the invention is not limited to the embodiment described but encompasses any variant falling within the scope of the invention as defined by the claims.

In particular, the inverter may have a structure different from that described.

Any type of switch can be used and in particular any type of transistor.

The inverter can be of a different type and for example have a number of different levels: for example two levels but the number is preferably at least equal to three or even five levels, which makes it possible to leave floating potentials and improves the performance of the inverter.

The resonant cell may have another structure than that described. Thus, the resonant cell here comprises only passive electronic components, which is advantageous in terms of complexity and cost, but the resonant cell may comprise, as a variant, at least one active component.

The variant of figure 5, which makes it possible to vary the resonance frequency to adapt it to the chopping frequency, is optional.

Claims (7)

Multilevel inverter, comprising a set of capacitors (C) having a plurality of connection points and a set of switches (S1 to S6) arranged and connected to a control unit (UC) to successively connect each of the connection points with a first output line thus subjected to an alternating output voltage, characterized in that the set of switches comprises two parallel branches on which are respectively mounted a first inductor (L1) and a second inductor (L2) and between which are connected a first capacitor (C1) and a second capacitor (C2) to form a resonant cell subjected to the AC output voltage, the first capacitor and the second capacitor being connected to the branches in a crossed manner on either side of the inductors. Inverter according to claim 1, comprising a first branch and a second branch connected in parallel to a positive connection point (+DC) and a negative connection point (-DC), the first branch comprising two capacitors (C) connected in series at the positive connection point (+DC) and at the negative connection point (–DC), the second branch comprising in series a first pair of transistors (S1, S2) and a second pair of transistors (S4, S6), a third branch being connected to the midpoint of the first pair of transistors (S1, S2) and a fourth branch being connected to the midpoint of the second pair of transistors (S4, S6), the third branch and the fourth branch respectively comprising a first assembly of transistors (S3) and a second assembly of transistors (S5) and being both connected to the first output line, a second output line being connected to the midpoint of the second leg and to the midpoint of the first leg to define the output voltage (Vout) with the first output line. Inverter according to Claim 2, in which: the first inductor (L1) is mounted on the third branch, the second inductor (L2) is mounted on the fourth branch, the first capacitor (C1) is connected to a first terminal of the first inductor on the side of the first pair of transistors (S1, S2) and to a second terminal of the second inductor on the side of the second assembly of transistors (S5), and the second capacitor (C2) is connected to a first terminal of the second inductor on the side of the second pair of transistors (S4, S6) and to a second terminal of the first inductor on the side of the first assembly of transistors (S3). Inverter according to claim 3, comprising a fifth branch in parallel with the third branch and a sixth branch in parallel with the fourth branch, the fifth branch comprising a third inductance (L3) and a third transistor assembly (S7) and the sixth branch comprising a fourth inductor (L4) and a fourth transistor arrangement (S8). Inverter according to any one of Claims 2 to 4, in which the control unit is arranged to drive the transistors as follows:
-the first transistor (S1) of the first pair is driven by a square wave signal, the second transistor (S2) of the first pair is driven by a square wave signal in phase opposition with the previous one, the first assembly of transistors (S3) and the third transistor (S4) of the second pair are on, the second transistor assembly (S5) and the fourth transistor (S6) of the second pair are off so that the output voltage (Vout) is positive;
-the fourth transistor (S6) is driven by a square wave signal, the first transistor assembly (S3) and the third transistor (S4) are driven by a square wave signal in phase opposition with the previous one, the second transistor (S2) and the second assembly of transistors (S5) are on, the first transistor (S1) and the first assembly of transistors (S3) are off so that the output voltage (Vout) is negative. Inverter according to Claim 1, in which the resonant cell comprises only passive electronic components. Inverter according to any one of the preceding claims, in which the resonant cell has an overall induction and an overall capacitance such that the resonant frequency is lower than a switching frequency of the inverter.