WO2021165231A1

WO2021165231A1 - Multilevel inverter having a resonant cell

Info

Publication number: WO2021165231A1
Application number: PCT/EP2021/053721
Authority: WO
Inventors: Louis GRIMAUD
Original assignee: Safran Electronics & Defense
Priority date: 2020-02-17
Filing date: 2021-02-16
Publication date: 2021-08-26
Also published as: FR3107407A1; FR3107407B1

Abstract

Multilevel inverter, comprising a set of capacitors (C) having a plurality of connection points and a set of switches (S1 to S6) arranged and connected to a control unit (UC) so as to successively connect each of the connection points to a first output line thus subjected to an alternating output voltage. The set of switches comprises two parallel branches on which a first inductor (L1) and a second inductor (L2) are respectively mounted and between which a first capacitor (C1) and a second capacitor (C2) are connected to form a resonant cell subjected to the alternating output voltage, the first capacitor and the second capacitor being cross-connected to the branches on either side of the inductors.

Description

MULTI-LEVEL RESONANT CELL INVERTER

BACKGROUND OF THE INVENTION

The present invention relates to the field of the conversion of electrical energy and more particularly to electrical power converters such as inverters.

Inverters are conventionally used to supply electrical equipment, such as an electric motor, with alternating current / voltage from a direct current / voltage source.

An inverter is an electrical circuit arranged to output a sine wave having predetermined characteristics of amplitude, frequency and harmonic content. The wave should be as sinusoidal as possible. Indeed, the imperfections of the sinusoidal voltage generate a distortion of the harmonic current. This distortion increases the losses and causes the motor to heat up considerably.

There are many UPS topologies, each resulting from a trade-off between complexity and performance.

Among these topologies, one can distinguish the inverters with controlled switching which comprise a particular arrangement of switches which are controlled to provide a sine wave of variable amplitude and frequency.

An example of a voltage source controlled switching inverter is shown in FIG. 1, namely a multilevel inverter and more particularly here with three ANPC levels. This inverter comprises a first branch and a second branch connected in parallel to a positive + DC connection point and a negative - DC connection point. The first branch comprises two capacitors C connected in series to the positive connection point + DC and to the negative connection point -DC. The second branch comprises in series a first pair of transistors S1, S2 and a second pair of transistors S4, S6, the transistor S1 being connected to the positive + DC connection point and the transistor S6 being connected to the negative connection point - DC. A third branch is connected to the midpoint of the first pair of transistors S1, S2 and a fourth branch is connected to the midpoint of the second pair of transistors S4, S6. The third branch and the fourth branch respectively comprise a fifth transistor S3 and a sixth transistor S5 and are both connected to a first output line having an inductance Lf. A second output line is connected to the midpoint of the second branch (between the two pairs of transistors) and to the midpoint of the first branch (between the two capacitors C1, C2) to define with the first output line a voltage of Vout exit. The transistors SI to S6 are driven by a control circuit, not shown, according to a predetermined modulation law. An example of the law of modulation of transistors is represented in FIG. 2 which shows that: - the output voltage Vout is positive when the transistor SI is driven by a square signal, the transistors S2 and S5 are driven by a square signal in opposition in phase with the previous one, transistors S3 and S4 are on, transistor S6 is blocked / open; - the output voltage Vout is negative when the transistor S6 is driven by a square signal, the transistors S3 and S4 are driven by a square signal in phase opposition with the previous one, the transistors S2 and S5 are on, the transistor SI is blocked / open. Square waves are usually operated as a series of pulses whose width is modulated to define the amplitude and frequency of the output voltage.

Controlled switching inverters have two main drawbacks, namely: switching losses on the one hand and strong voltage fronts (dV / dt) at the output generating electromagnetic disturbances on the other hand. These drawbacks are all the more troublesome as the desired output frequency is high. OBJECT OF THE INVENTION

The object of the invention is in particular to improve the performance of inverters with controlled switching.

SUMMARY OF THE INVENTION

For this purpose, according to the invention, a multilevel inverter is provided, comprising a set of capacitors having a plurality of connection points and a set of switches arranged and connected to a control unit for successively connecting each of the connection points with a first output line thus subjected to an alternating output voltage. The set of switches comprises two parallel branches on which are respectively mounted a first inductor and a second inductor and between which are connected a first capacitor and a second capacitor to form a resonant cell subjected to the alternating output voltage, the first capacitor and the second capacitor being connected to the branches in a crossed manner on either side of the inductors.

Thus, the resonant cell forms a Z-shaped filter capable of absorbing all or part of the voltage fronts so that the inverter does not generate electromagnetic disturbances downstream.

Preferably, the inverter is a three-level inverter in which: the first inductor is mounted on the third branch, the second inductor is mounted on the fourth branch, the first capacitor is connected to a first terminal of the first inductor on the side of the first pair of transistors and to a second terminal of the second inductor on the side of the second transistor assembly, and the second capacitor is connected to a first terminal of the second inductor on the side of the second pair of transistors and to a second terminal of the first inductor on the side of the first transistor assembly. With this topology, the inverter allows a modulation strategy favoring soft switching, that is to say at 0V, while eliminating voltage edges on the output line.

Advantageously, the inverter comprises a fifth branch in parallel with the third branch and a sixth branch in parallel with the fourth branch, the fifth branch comprising a third inductor and a third assembly of transistors and the sixth branch comprising a fourth inductor and a fourth. assembly of transistors.

This makes it possible to double the inductance value seen by the resonance current and therefore to play on the resonant frequency of the resonant cell.

Preferably, the control unit is arranged to drive the transistors as follows: the first transistor is driven by a square signal, the second transistor is driven by a square signal in phase opposition with the previous one, the first transistor assembly and the third transistor are on, the second assembly of transistors and the fourth transistor are blocking so that the output voltage is positive; the fourth transistor is driven by a square signal, the first assembly of transistors and the third transistor are driven by a square signal in phase opposition with the previous one, the second transistor and the second assembly of transistors are conductive, the first transistor and the first assembly of transistors are blocking so that the output voltage is negative. This control mode makes it possible to suppress strong variations in the voltage of the inverter.

Other characteristics and advantages of the invention will emerge on reading the following description of a particular and non-limiting embodiment of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS Reference will be made to the accompanying drawings, among which: FIG. 1 is a diagram of a three-level inverter of the prior art;

FIG. 2 is a diagram illustrating the control law of this three-level inverter of the prior art;

FIG. 3 is a diagram of a three-level inverter according to the invention;

FIG. 4 is a diagram illustrating the control law of the inverter according to the invention;

FIG. 5 is a diagram of a three-level inverter according to a variant of the invention. DETAILED DESCRIPTION OF THE INVENTION

The invention is an inverter which can be used for controlling any actuator such as a motor having one or more phases. The connection of the inverter to the actuator and the adaptation of the inverter to the actuator (number of phases in particular) are known in themselves and will not be described here.

With reference to FIG. 3, the inverter according to the invention comprises a first branch and a second branch connected in parallel to a positive connection point + DC and a negative connection point -DC.

The first branch comprises two capacitors C connected in series to the positive connection point + DC and to the negative connection point -DC.

The second branch comprises in series a first pair of transistors S1, S2 and a second pair of transistors S4, S6. The transistors S1, S2, S4, S6 are here MOSFET type field effect transistors (note that it would be possible to use transistors of different type: IGBT, HEMT, etc.). The first transistor S1 has a drain connected to the positive + DC terminal and a source connected to the drain of the second transistor S2, the source of which is connected to the drain of the third transistor S4. The source of the third transistor S4 is connected to the drain of the fourth transistor S6 which has a source connected to the negative terminal -DC. The second branch has a midpoint (between the two pairs of transistors) which is connected to a midpoint of the first branch (between the capacitors C) which forms a third connection point. The inverter comprises a third branch connected to the midpoint of the first pair of transistors S1, S2 and a fourth branch connected to the midpoint of the second pair of transistors S4, S6. The third branch and the fourth branch respectively comprise a first assembly of transistors S3 comprising two transistors mounted at a common drain, and a second assembly of transistors S5 comprising two transistors mounted at a common drain. The third branch and the fourth branch are both connected to a first output line. The transistors of the first assembly of transistors S3 and of the second assembly of transistors S5 are here MOSFET type field effect transistors.

The inverter comprises a second output line connected to the midpoint of the first branch to define with the first output line an output voltage Vout.

The inverter includes a resonant cell mounted in the switch assembly to be subjected to an alternating voltage.

The resonant cell comprises a first inductor L1 mounted on the third branch and a second inductor L2 mounted on the fourth branch. The inductors L1 and L2 have the same value corresponding to the overall inductance of the resonant cell. A first capacitor C1 is connected to a first terminal of the first inductor L1 on the side of the first pair of transistors S1, S2 and to a second terminal of the second inductance L2 on the side of the second assembly of transistors S5. A second capacitor C2 is connected to a first terminal of the second inductor L2 on the side of the second pair of transistors S4, S6 and to a second terminal of the first inductance L1 on the side of the first assembly of transistors S3. The capacitors C1, C2 are thus connected to the third branch and to the fourth branch in a crossed manner on either side of the inductors L1, L2 to form with the inductors L1, L2 a resonant circuit of the “Z source” type. Capacitors C1 and C2 have the same value corresponding to the overall capacity of the resonant cell.

The control unit UC is arranged to drive the transistors S1 to S6 as follows (see FIG. 4):

- the first transistor SI is driven by a square signal at a switching frequency, the second transistor S2 is driven by a square signal in phase opposition with the previous one, the first assembly of transistors S3 and the third transistor

54 are on, the second assembly of transistors

55 and the fourth transistor S6 are blocking so that the output voltage Vout is positive;

- the fourth transistor S6 is driven by a square signal at the switching frequency, the first assembly of transistors S3 and the third transistor S4 are driven by a square signal in phase opposition with the previous one, the second transistor S2 and the second assembly of transistors S5 are on, the first transistor SI and the first assembly of transistors S3 are blocking so that the output voltage Vout is negative.

Depending on the switching frequency with respect to the resonant frequency of the source Z cell, it is possible to guarantee that the current changes sign before the transistor is turned ON to allow voltage switching to zero. This control mode allows gentle switching of the transistors.

The inverter device is in practice connected to a DC voltage source or to a rectifier bridge in such a way that the capacitors C are always supplied.

It will be understood that the transistors SI to S6 form a group of switches arranged and controlled to successively connect each of the connection points with the first output line which is thus subjected to an alternating output voltage. The AC output voltage has characteristics depending on the switching frequency.

The shape of the output voltage is all the more sinusoidal the closer the resonant frequency is to the switching frequency. In addition, the gain is also greater in this case. On the other hand, the switching frequency must be greater than the resonant frequency in order to benefit from switching at zero volts. We therefore choose the values of inductors L1 and L2 and the value of capacitors Cl and C2 so that the resonant frequency is lower than the switching frequency and to minimize the average value of the resonant current and maximize the switching duty cycle interval at zero voltage.

The invention has several significant advantages: it allows the control of much faster motors (speed between 0 and 50.10e3 rad / s), it allows an increase in the frequency without increasing the volume of the electronics (gain on the cooling, on filters and decoupling capacities), it makes it possible to separate the power electronics and the motor, allowing a relaxation of the environmental constraints of the electronics, it limits or even eliminates the aging problems of the motors (insulator) caused by partial discharges, it limits or even eliminates the problems of electromagnetic radiation downstream of the inverter, and therefore the use of shielding to the detriment of mass and cost.

In the variant of FIG. 5, the inverter comprises a fifth branch in parallel with the third branch and a sixth branch in parallel with the fourth branch. The fifth branch comprises a third inductor L3 and a third circuit of transistors S7 and the sixth branch comprises a fourth inductor L4 and a fourth circuit of transistors S8. The transistors of the third set of transistors S7 and of the fourth set of transistors S8 are controlled statically by the control unit UC. The third assembly of transistors S7 and the fourth assembly of transistors S8 are on and off at the same time as the first assembly of transistors S3 and the second assembly of transistors S5 if the conditions are satisfied at the level of the command.

Of course, the invention is not limited to the embodiment described but encompasses any variant coming within the scope of the invention as defined by the claims. In particular, the inverter can have a structure different from that described.

Any type of switch can be used and in particular any type of transistor.

The inverter can be of different type and for example have a number of different levels: for example two levels but the number is preferably at least equal to three or even five levels, which makes it possible to leave potentials floating and improves the performance of the inverter.

The resonant cell can have a structure other than that described. Thus, the resonant cell here comprises only passive electronic components, which is advantageous in terms of complexity and cost, but the resonant cell can comprise, as a variant, at least one active component. The variant of FIG. 5, which makes it possible to vary the resonant frequency in order to adapt it to the chopping frequency, is optional.

Claims

1. Multi-level inverter, comprising a set of capacitors (C) having a plurality of connection points and a set of switches (SI to S6) arranged and connected to a control unit (UC) for successively connecting each of the connection points with a first output line thus subjected to an alternating output voltage, characterized in that the set of switches comprises two parallel branches on which are respectively mounted a first inductor (Ll) and a second inductor (L2) and between which a first capacitor (Cl) and a second capacitor (C2) are connected to form a resonant cell subjected to the alternating output voltage, the first capacitor and the second capacitor being connected to the branches in a crossed manner on either side of the inductors .

2. An inverter according to claim 1, comprising a first branch and a second branch connected in parallel to a positive connection point (+ DC) and a negative connection point (-DC), the first branch comprising two capacitors (C) connected. in series at the positive connection point (+ DC) and at the negative connection point (-DC), the second branch comprising in series a first pair of transistors (SI, S2) and a second pair of transistors (S4, S6), a third branch being connected to the midpoint of the first pair of transistors (S1, S2) and a fourth branch being connected to the midpoint of the second pair of transistors (S4, S6), the third branch and the fourth branch respectively comprising a first assembly of transistors (S3) and a second assembly of transistors (S5) and both being connected to the first output line, a second output line being connected to the midpoint of the second branch and to the midpoint of the first branch to define the output voltage (Vout ) with the first line of output.

3. An inverter according to claim 2, wherein: the first inductor (Ll) is mounted on the third branch, the second inductor (L2) is mounted on the fourth branch, the first capacitor (Cl) is connected to a first terminal of the first inductor on the side of the first pair of transistors (S1, S2) and to a second terminal of the second inductor on the side of the second assembly of transistors (S5), and the second capacitor (C2) is connected to a first terminal of the second inductor on the side of the second pair of transistors (S4, S6) and to a second terminal of the first inductor on the side of the first transistor assembly (S3).

4. An inverter according to claim 3, comprising a fifth branch in parallel with the third branch and a sixth branch in parallel with the fourth branch, the fifth branch comprising a third inductor (L3) and a third assembly of transistors (S7) and the sixth branch comprising a fourth inductor (L4) and a fourth assembly of transistors (S8).

5. An inverter according to any one of claims 2 to 4, wherein the control unit is arranged to drive the transistors as follows:

-the first transistor (SI) of the first pair is driven by a square signal, the second transistor (S2) of the first pair is driven by a square signal in phase opposition with the previous one, the first assembly of transistors (S3) and the third transistor (S4) of the second pair are on, the second assembly of transistors (S5) and the fourth transistor (S6) of the second pair are blocking so that the output voltage (Vout) is positive;

-the fourth transistor (S6) is driven by a square signal, the first assembly of transistors (S3) and the third transistor (S4) are driven by a square signal in phase opposition with the previous one, the second transistor (S2) and the second assembly of transistors (S5) are on, the first transistor (SI) and the first assembly of transistors (S3) are blocking so that the output voltage (Vout) is negative.

6. An inverter according to claim 1, wherein the resonant cell comprises only passive electronic components.

7. An inverter according to any one of the preceding claims, in which the resonant cell has an overall induction and an overall capacity such that the resonant frequency is lower than a switching frequency of the inverter.