FR3092467B1 - Procédé de fabrication d’une carte micromodules haute densité - Google Patents
Procédé de fabrication d’une carte micromodules haute densité Download PDFInfo
- Publication number
- FR3092467B1 FR3092467B1 FR1900914A FR1900914A FR3092467B1 FR 3092467 B1 FR3092467 B1 FR 3092467B1 FR 1900914 A FR1900914 A FR 1900914A FR 1900914 A FR1900914 A FR 1900914A FR 3092467 B1 FR3092467 B1 FR 3092467B1
- Authority
- FR
- France
- Prior art keywords
- card
- micromodule
- manufacturing process
- high density
- electronic card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000463 material Substances 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1712—Layout
- H01L2224/1713—Square or rectangular array
- H01L2224/17132—Square or rectangular array being non uniform, i.e. having a non uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1712—Layout
- H01L2224/1713—Square or rectangular array
- H01L2224/17134—Square or rectangular array covering only portions of the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/142—HF devices
- H01L2924/1421—RF devices
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10234—Metallic balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Combinations Of Printed Boards (AREA)
- Credit Cards Or The Like (AREA)
Abstract
Procédé de fabrication d’une carte électronique et sa carte électronique comprenant une carte mère sur laquelle on dépose une ou plusieurs cartes filles (MHD1) caractérisé en ce que l’on utilise une matrice de billes Bi disposée sur une surface Sm donnée et située entre la carte mère (1) et au moins une carte fille (MHD1), la géométrie, la disposition et le matériau des billes étant choisis en fonction des fonctionnalités de la carte électronique. Figure pour l’abrégé : Fig. 2
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1900914A FR3092467B1 (fr) | 2019-01-31 | 2019-01-31 | Procédé de fabrication d’une carte micromodules haute densité |
PCT/EP2020/052494 WO2020157315A1 (fr) | 2019-01-31 | 2020-01-31 | Procede de fabrication d'une carte micromodules haute densite |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1900914 | 2019-01-31 | ||
FR1900914A FR3092467B1 (fr) | 2019-01-31 | 2019-01-31 | Procédé de fabrication d’une carte micromodules haute densité |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3092467A1 FR3092467A1 (fr) | 2020-08-07 |
FR3092467B1 true FR3092467B1 (fr) | 2021-07-16 |
Family
ID=67441230
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1900914A Active FR3092467B1 (fr) | 2019-01-31 | 2019-01-31 | Procédé de fabrication d’une carte micromodules haute densité |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR3092467B1 (fr) |
WO (1) | WO2020157315A1 (fr) |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998048602A1 (fr) * | 1997-04-21 | 1998-10-29 | Lsi Logic Corporation | Ensemble boitier a grille de globules comprenant des pieces d'ecartement |
TWI234209B (en) * | 2003-10-31 | 2005-06-11 | Advanced Semiconductor Eng | BGA semiconductor device with protection of component on ball-planting surface |
US7445141B2 (en) * | 2004-09-22 | 2008-11-04 | International Business Machines Corporation | Solder interconnection array with optimal mechanical integrity |
TWI361482B (en) * | 2007-05-10 | 2012-04-01 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor package structure and package substrate applicable thereto |
KR20120060960A (ko) * | 2010-09-20 | 2012-06-12 | 삼성전자주식회사 | 반도체 패키지, 전자 장치 및 이를 채택하는 전자 시스템 |
JP2014082281A (ja) * | 2012-10-15 | 2014-05-08 | Olympus Corp | 基板、半導体装置、基板の製造方法 |
US9018040B2 (en) * | 2013-09-30 | 2015-04-28 | International Business Machines Corporation | Power distribution for 3D semiconductor package |
US9437551B2 (en) * | 2014-02-13 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Concentric bump design for the alignment in die stacking |
FI127701B (en) * | 2015-05-25 | 2018-12-31 | Maekelae Raimo | Radio frequency module and circuit board |
KR102366970B1 (ko) * | 2017-05-16 | 2022-02-24 | 삼성전자주식회사 | 반도체 패키지 |
-
2019
- 2019-01-31 FR FR1900914A patent/FR3092467B1/fr active Active
-
2020
- 2020-01-31 WO PCT/EP2020/052494 patent/WO2020157315A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2020157315A1 (fr) | 2020-08-06 |
FR3092467A1 (fr) | 2020-08-07 |
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PLFP | Fee payment |
Year of fee payment: 2 |
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Effective date: 20200807 |
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Year of fee payment: 3 |
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