FR3061565B1 - Fonctionnement d'un microcontroleur en mode basse puissance - Google Patents
Fonctionnement d'un microcontroleur en mode basse puissance Download PDFInfo
- Publication number
- FR3061565B1 FR3061565B1 FR1750058A FR1750058A FR3061565B1 FR 3061565 B1 FR3061565 B1 FR 3061565B1 FR 1750058 A FR1750058 A FR 1750058A FR 1750058 A FR1750058 A FR 1750058A FR 3061565 B1 FR3061565 B1 FR 3061565B1
- Authority
- FR
- France
- Prior art keywords
- interrupt signal
- microcontroller
- low power
- processor
- power mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Power Sources (AREA)
- Microcomputers (AREA)
Abstract
L'invention concerne un système comprenant : des premier (CPUO) et second (CPU1) processeurs, le second étant capable de traiter uniquement un sous-ensemble du jeu d'instructions traitable par le premier ; un circuit de gestion de puissance (2) adapté à sélectionner l'un ou l'autre des premier et second processeurs (CPUO, CPU1) et à le rendre actif ou le mettre en veille ; un premier périphérique (4) adapté à générer un signal d'interruption ; un commutateur (8) adapté à diriger le signal d'interruption soit vers le premier processeur, soit vers le second processeur, selon celui qui est sélectionné ; et une première mémoire (12) adaptée à stocker une routine d'interruption associée au signal d'interruption, le processeur actif étant adapté à exécuter cette routine d'interruption en réponse au signal d'interruption.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1750058A FR3061565B1 (fr) | 2017-01-04 | 2017-01-04 | Fonctionnement d'un microcontroleur en mode basse puissance |
CN201710763010.4A CN108268118B (zh) | 2017-01-04 | 2017-08-30 | 用于操作微控制器的系统和方法 |
CN201721098246.2U CN207232886U (zh) | 2017-01-04 | 2017-08-30 | 电子系统 |
US15/701,003 US10402353B2 (en) | 2017-01-04 | 2017-09-11 | System and method for processing interrupts by processors of a microcontroller in a low-power mode |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1750058A FR3061565B1 (fr) | 2017-01-04 | 2017-01-04 | Fonctionnement d'un microcontroleur en mode basse puissance |
FR1750058 | 2017-01-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3061565A1 FR3061565A1 (fr) | 2018-07-06 |
FR3061565B1 true FR3061565B1 (fr) | 2019-04-26 |
Family
ID=58645187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1750058A Expired - Fee Related FR3061565B1 (fr) | 2017-01-04 | 2017-01-04 | Fonctionnement d'un microcontroleur en mode basse puissance |
Country Status (3)
Country | Link |
---|---|
US (1) | US10402353B2 (fr) |
CN (2) | CN108268118B (fr) |
FR (1) | FR3061565B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7383589B2 (ja) * | 2020-09-23 | 2023-11-20 | 株式会社東芝 | 情報処理装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5666537A (en) * | 1994-08-12 | 1997-09-09 | Intel Corporation | Power down scheme for idle processor components |
TW591525B (en) * | 2003-03-07 | 2004-06-11 | Novatek Microelectronics Corp | Interrupt-processing system for shortening interrupt latency in microprocessor |
WO2006013857A1 (fr) * | 2004-08-05 | 2006-02-09 | Matsushita Electric Industrial Co., Ltd. | Dispositif de traitement d’informations |
JP2006243865A (ja) * | 2005-03-01 | 2006-09-14 | Seiko Epson Corp | プロセッサおよび情報処理方法 |
CN103064756B (zh) * | 2011-10-21 | 2016-07-06 | 晨星软件研发(深圳)有限公司 | 电子系统及其存储器管理方法 |
CN103544125B (zh) * | 2012-07-12 | 2017-02-22 | 深圳市中兴微电子技术有限公司 | 中断的控制方法、中断的处理方法、中断控制器和处理器 |
US9009508B2 (en) * | 2012-08-28 | 2015-04-14 | Advanced Micro Devices, Inc. | Mechanism for reducing interrupt latency and power consumption using heterogeneous cores |
JP6303670B2 (ja) * | 2014-03-19 | 2018-04-04 | 日本電気株式会社 | 複数cpuの起動回路、複数cpuの起動方法及び複数cpuの起動回路のプログラム |
KR102187912B1 (ko) * | 2014-09-26 | 2020-12-07 | 인텔 코포레이션 | 인터럽트들의 세트들을 구성하는 장치 및 방법 |
-
2017
- 2017-01-04 FR FR1750058A patent/FR3061565B1/fr not_active Expired - Fee Related
- 2017-08-30 CN CN201710763010.4A patent/CN108268118B/zh active Active
- 2017-08-30 CN CN201721098246.2U patent/CN207232886U/zh active Active
- 2017-09-11 US US15/701,003 patent/US10402353B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20180189205A1 (en) | 2018-07-05 |
CN108268118A (zh) | 2018-07-10 |
CN207232886U (zh) | 2018-04-13 |
FR3061565A1 (fr) | 2018-07-06 |
US10402353B2 (en) | 2019-09-03 |
CN108268118B (zh) | 2021-07-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Search report ready |
Effective date: 20180706 |
|
PLFP | Fee payment |
Year of fee payment: 4 |
|
ST | Notification of lapse |
Effective date: 20210905 |