FR3007186B1 - Dispositif de memoire compact associant un plan memoire du type sram et un plan memoire du type non volatil, et procedes de fonctionnement - Google Patents

Dispositif de memoire compact associant un plan memoire du type sram et un plan memoire du type non volatil, et procedes de fonctionnement

Info

Publication number
FR3007186B1
FR3007186B1 FR1355440A FR1355440A FR3007186B1 FR 3007186 B1 FR3007186 B1 FR 3007186B1 FR 1355440 A FR1355440 A FR 1355440A FR 1355440 A FR1355440 A FR 1355440A FR 3007186 B1 FR3007186 B1 FR 3007186B1
Authority
FR
France
Prior art keywords
memory
plan
type
methods
compact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1355440A
Other languages
English (en)
Other versions
FR3007186A1 (fr
Inventor
Francois Tailliet
Marc Battista
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1355440A priority Critical patent/FR3007186B1/fr
Priority to US14/296,014 priority patent/US9245627B2/en
Publication of FR3007186A1 publication Critical patent/FR3007186A1/fr
Application granted granted Critical
Publication of FR3007186B1 publication Critical patent/FR3007186B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0063—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G11C14/0018—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
FR1355440A 2013-06-12 2013-06-12 Dispositif de memoire compact associant un plan memoire du type sram et un plan memoire du type non volatil, et procedes de fonctionnement Expired - Fee Related FR3007186B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1355440A FR3007186B1 (fr) 2013-06-12 2013-06-12 Dispositif de memoire compact associant un plan memoire du type sram et un plan memoire du type non volatil, et procedes de fonctionnement
US14/296,014 US9245627B2 (en) 2013-06-12 2014-06-04 Compact memory device including a SRAM memory plane and a non volatile memory plane, and operating methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1355440A FR3007186B1 (fr) 2013-06-12 2013-06-12 Dispositif de memoire compact associant un plan memoire du type sram et un plan memoire du type non volatil, et procedes de fonctionnement

Publications (2)

Publication Number Publication Date
FR3007186A1 FR3007186A1 (fr) 2014-12-19
FR3007186B1 true FR3007186B1 (fr) 2016-09-09

Family

ID=48874399

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1355440A Expired - Fee Related FR3007186B1 (fr) 2013-06-12 2013-06-12 Dispositif de memoire compact associant un plan memoire du type sram et un plan memoire du type non volatil, et procedes de fonctionnement

Country Status (2)

Country Link
US (1) US9245627B2 (fr)
FR (1) FR3007186B1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3018944A1 (fr) 2014-03-21 2015-09-25 St Microelectronics Rousset Dispositif de memoire associant un plan memoire du type sram et un plan-memoire du type non volatil, durci contre des basculements accidentels
FR3018952B1 (fr) * 2014-03-21 2016-04-15 Stmicroelectronics Rousset Structure integree comportant des transistors mos voisins
US9646694B2 (en) * 2014-10-21 2017-05-09 Cypress Semiconductor Corporation 10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof
US10706928B2 (en) * 2018-07-24 2020-07-07 Stmicroelectronics (Rousset) Sas Non-volatile static random access memory architecture having single non-volatile bit per volatile memory bit
US10614879B2 (en) 2018-07-24 2020-04-07 Stmicroelectronics (Rousset) Sas Extended write modes for non-volatile static random access memory architectures having word level switches
FR3106692B1 (fr) 2020-01-27 2024-01-19 St Microelectronics Rousset Dispositif de mémoire vive statique non-volatile et procédé de commande correspondant.
FR3107971B1 (fr) * 2020-03-03 2022-02-18 St Microelectronics Rousset Procédé d’écriture de données dans une mémoire d’un transpondeur sans contact, et dispositif de transpondeur sans contact correspondant.

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2645491A1 (de) 1976-10-08 1978-05-11 Vdo Schindling Schaltungsanordnung zum steuern eines vorwaerts-rueckwaerts-zaehlers
US4467451A (en) 1981-12-07 1984-08-21 Hughes Aircraft Company Nonvolatile random access memory cell
JPS62217493A (ja) * 1986-02-27 1987-09-24 Fujitsu Ltd 半導体不揮発性記憶装置
US4980859A (en) 1989-04-07 1990-12-25 Xicor, Inc. NOVRAM cell using two differential decouplable nonvolatile memory elements
JP3020345B2 (ja) * 1992-05-19 2000-03-15 株式会社 沖マイクロデザイン 半導体記憶回路
US5519663A (en) 1994-09-28 1996-05-21 Sci Systems, Inc. Preservation system for volatile memory with nonvolatile backup memory
JP3059076B2 (ja) * 1995-06-19 2000-07-04 シャープ株式会社 不揮発性半導体記憶装置
DE19858755C1 (de) * 1998-12-18 2000-06-08 Euro Matsushita Electric Works Kontakteinheit für elektromagnetische Relais
US6469930B1 (en) * 2000-10-30 2002-10-22 Cypress Semiconductor Corporation Compact nonvolatile circuit having margin testing capability
US7092293B1 (en) * 2003-11-25 2006-08-15 Xilinx, Inc. Non-volatile memory cell integrated with a latch
US7164608B2 (en) 2004-07-28 2007-01-16 Aplus Flash Technology, Inc. NVRAM memory cell architecture that integrates conventional SRAM and flash cells
US8331150B2 (en) * 2008-01-03 2012-12-11 Aplus Flash Technology, Inc. Integrated SRAM and FLOTOX EEPROM memory device
US8018768B2 (en) 2009-08-18 2011-09-13 United Microelectronics Corp. Non-volatile static random access memory (NVSRAM) device

Also Published As

Publication number Publication date
US9245627B2 (en) 2016-01-26
US20140369119A1 (en) 2014-12-18
FR3007186A1 (fr) 2014-12-19

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