FR3005786A1 - Circuit cascode a deux transistors - Google Patents

Circuit cascode a deux transistors Download PDF

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Publication number
FR3005786A1
FR3005786A1 FR1354299A FR1354299A FR3005786A1 FR 3005786 A1 FR3005786 A1 FR 3005786A1 FR 1354299 A FR1354299 A FR 1354299A FR 1354299 A FR1354299 A FR 1354299A FR 3005786 A1 FR3005786 A1 FR 3005786A1
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FR
France
Prior art keywords
transistor
transistors
cascode
circuit
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR1354299A
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English (en)
Inventor
Vincent Knopik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
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STMicroelectronics SA
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Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR1354299A priority Critical patent/FR3005786A1/fr
Priority to FR1358322A priority patent/FR3005787A1/fr
Publication of FR3005786A1 publication Critical patent/FR3005786A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un circuit cascode comportant un premier transistor et un deuxième transistor MOS en série, dans lequel la source du premier transistor est reliée au drain du deuxième transistor par une zone semiconductrice dopée.

Description

B12666 - 13-GR1-0399 1 CIRCUIT CASCODE À DEUX TRANSISTORS Domaine La présente description concerne, de façon générale, les circuits électroniques et, plus particulièrement la réalisation d'un circuit cascode à base de transistors MOS.
Exposé de l'art antérieur Les circuits ou montages cascode sont généralement formés de transistors connectés en série. Résumé Un mode de réalisation de la présente description vise 10 à pallier tout ou partie des inconvénients des circuits cascode connus. Ainsi, un mode de réalisation prévoit un circuit comportant un premier transistor et un deuxième transistor MOS en série, dans lequel la source du premier transistor est reliée 15 au drain du deuxième transistor par une zone semiconductrice dopée. Selon un mode de réalisation, la liaison entre source et drain des premier et deuxième transistors est exclusivement formée par une zone en matériau semiconducteur dopé. 20 Brève description des dessins Ces caractéristiques et avantages, ainsi que d'autres, seront exposés en détail dans la description suivante de modes B12666 - 13-GR1-0399 2 de réalisation particuliers faite à titre non limitatif en relation avec les figures jointes qui illustrent la structure, la réalisation et le fonctionnement d'un mode de réalisation d'un circuit cascode à deux transistors.
Description détaillée Par souci de clarté, de mêmes éléments ont été désignés par de mêmes références aux différentes figures et, de plus, comme cela est habituel dans la représentation des circuits intégrés, les diverses figures ne sont pas tracées à l'échelle. La figure 1 est une représentation schématique tridimensionnelle d'un mode de réalisation d'un circuit cascode à deux transistors. Dans cet exemple, le circuit est réalisé avec des 15 transistors à déplétion totale sur substrat SOI (silicium sur isolant), ou transistors FDSOI. En figure 1, le substrat massif sous la couche isolante enterrée BOX (Burried Oxide Layer) n'a pas été représenté. 20 Les éléments représentés aux figures sont : une couche semiconductrice 11 dans laquelle sont formés les transistors, au dessus de la couche BOX ; dans la couche 11 : une région de drain d'un premier transistor M2 ; 25 une région NDRIFT ; une région PBODY ; des régions PLUS ; une région dopée de type N, A, connectant directement les deux transistors (formant la source du transistor M2 et le 30 drain du transistor Ml) ; un caisson P, PWELL ; une région de source NPLUS du deuxième transistor Ml ; des régions PLUS ; au-dessus de la couche 11 : 35 un oxyde de grille Gate Oxide ; B12666 - 13-GR1-0399 3 des régions de grille Active Gate et Control Gate. Le cascode de la figure 1 est un dispositif cascode compact à deux transistors (dont un transistor MOS latéral à canal N). En connectant directement les transistors par une 5 région dopée A et sans métal, la résistance de la connexion est considérablement réduite. En éliminant la connexion métallique entre les deux transistors, la capacité parasite est réduite. De plus, le flux de courant devient direct entre les deux transistors (pas besoin de contact métallique, ni de piste 10 métallique). La figure 2 représente le schéma électrique du circuit de la figure 1. Sont référencés : les transistors Ml et M2 ; 15 le drain (Drain) du transistor M2 ; la source (Source) du transistor Ml ; la région commune A ; la grille (Control Gate) du transistor M2 ; la grille (Active Gate) du transistor Ml. 20 La figure 3 illustre le schéma équivalent du montage de la figure 1 en faisant ressortir les éléments capacitifs et résistifs, notamment liés aux métallisations. Un avantage de la structure proposée est de réduire les valeurs des éléments capacitifs parasites Cl et C2 et 25 résistifs. La figure 4 illustre le fonctionnement du circuit cascode compact. Les graphes de cette figure font ressortir des valeurs précises pour la tension de la grille de commande. 30 La figure 5 illustre les performances du circuit en fonctionnement à petit signaux. Cette figure fait ressortir les performances en termes de stabilité et de réponse en fréquence, par exemple aux environs de 2 GHz.
B12666 - 13-GR1-0399 4 La figure 6 illustre les performances du circuit en fonctionnement à grand signaux. Cette figure fait ressortir un gain en puissance de plus de 4 dB.
La figure 7 illustre la topologie d'un montage cascode usuel. La figure 8 illustre la topologie d'un mode de réalisation d'un montage cascode. La figure 9 illustre des étapes de fabrication d'un 10 cascode à deux transistors. Des modes de réalisation particuliers ont été décrits. Diverses variantes et modifications apparaîtront à l'homme de l'art. En particulier, bien que le cascode ait été décrit en relation avec une technologie FDSOI, cette réalisation 15 s'applique plus généralement à d'autres technologies.

Claims (3)

  1. REVENDICATIONS1. Circuit cascode comportant un premier transistor et un deuxième transistor MOS en série, dans lequel la source du premier transistor est reliée au drain du deuxième transistor par une zone semiconductrice dopée.
  2. 2. Circuit selon la revendication 1, dans lequel la liaison entre source et drain des premier et deuxième transistors est exclusivement formée par une zone en matériau semiconducteur dopé.
  3. 3. Circuit selon la revendication 1 ou 2, réalisé en 10 technologie FDSOI.
FR1354299A 2013-05-14 2013-05-14 Circuit cascode a deux transistors Withdrawn FR3005786A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1354299A FR3005786A1 (fr) 2013-05-14 2013-05-14 Circuit cascode a deux transistors
FR1358322A FR3005787A1 (fr) 2013-05-14 2013-08-30 Montage cascode de transistors pour l'amplification de signaux hautes frequences

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1354299A FR3005786A1 (fr) 2013-05-14 2013-05-14 Circuit cascode a deux transistors

Publications (1)

Publication Number Publication Date
FR3005786A1 true FR3005786A1 (fr) 2014-11-21

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FR1354299A Withdrawn FR3005786A1 (fr) 2013-05-14 2013-05-14 Circuit cascode a deux transistors
FR1358322A Pending FR3005787A1 (fr) 2013-05-14 2013-08-30 Montage cascode de transistors pour l'amplification de signaux hautes frequences

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FR1358322A Pending FR3005787A1 (fr) 2013-05-14 2013-08-30 Montage cascode de transistors pour l'amplification de signaux hautes frequences

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Publication number Priority date Publication date Assignee Title
US9842858B2 (en) 2015-11-18 2017-12-12 Peregrine Semiconductor Corporation Butted body contact for SOI transistor
CN109314132B (zh) * 2016-03-23 2021-10-29 派赛公司 用于soi晶体管的对接本体接触
US9837965B1 (en) 2016-09-16 2017-12-05 Peregrine Semiconductor Corporation Standby voltage condition for fast RF amplifier bias recovery
US9960737B1 (en) 2017-03-06 2018-05-01 Psemi Corporation Stacked PA power control

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040256692A1 (en) * 2003-06-19 2004-12-23 Keith Edmund Kunz Composite analog power transistor and method for making the same
JP5042518B2 (ja) * 2006-04-12 2012-10-03 ルネサスエレクトロニクス株式会社 半導体装置
US20080180160A1 (en) * 2007-01-31 2008-07-31 Infineon Technologies Ag High voltage dual gate cmos switching device and method
US7713821B2 (en) * 2007-06-25 2010-05-11 Sharp Laboratories Of America, Inc. Thin silicon-on-insulator high voltage auxiliary gated transistor

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FR3005787A1 (fr) 2014-11-21

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