FR2976711A1 - MEMORY CELL WITH VOLATILE AND NON-VOLATILE MEMORIZATION - Google Patents

Abstract

The invention relates to a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element (202) coupled between a first supply voltage (V, GND) and a first transistor of the first pair of transistors and programmed to have one of a first and a second resistance; and a control circuit adapted to store a data value (D) at the first and second storage nodes by coupling the first storage node to the second supply voltage (V, GND), the data value being determined by the programmed resistance of the first resistance switching element.

Description

B10704 - 03914-05 1 (e; T, T, MEMORY ULE WITH VOLATILE AND NON-VOLATILE STORAGE

FIELD OF THE INVENTION The present invention relates to a volatile / non-volatile memory cell, and a method of reading one or more non-volatile bits in a non-volatile memory cell. BACKGROUND OF THE INVENTION Figure 1 illustrates a typical Random Access Static Memory Cell (SRAM) 100. A first inverter consists of an N-channel MOS transistor (NMOS) 102 and a channel MOS transistor. P (PMOS) 103 connected in series between a supply voltage VDD and a ground voltage. A second inverter consists of an NMOS transistor 104 and a PMOS transistor 105, also connected in series between the supply voltage V DD and the ground voltage. The gates of the transistors 104 and 105 are coupled to a node 106 coupled to the drains of the transistors 102 and 103, while the gates of the transistors 102 and 103 are coupled to a node 108 coupled to the drains of the transistors 104 and 105, so that the Inverters constitute a flip-flop.

The nodes 106 and 108 store complementary voltage states Q and Q, for storing a data bit in the cell. Node 106 is coupled to a line of B10704 - 03914-05

2 bit BL via an N-channel MOS transistor (NMOS) 110, while the node 108 is coupled to a complementary bit line BLB via an NMOS transistor 112. The gates of the transistors 110 and 112 are coupled to a word line WL, and are activated by a low signal for writing or reading data in the cell 100. The circuit 100 has the advantage of being of rapid access during operations. reading and writing. However, a disadvantage is that, as with all volatile memory cells, the stored data is lost if the supply voltage VDD is removed. Flash memory is an example of programmable nonvolatile memory. A disadvantage of Flash memory is that it is relatively slow to access, compared to the SRAM cell of Figure 1, and requires a relatively high power supply voltage. In addition, Flash technology is difficult to integrate with CMOS technology, and has relatively low endurance. In many applications, there is a need for a programmable memory cell capable of storing nonvolatile data and having higher access speeds. SUMMARY OF THE INVENTION An object of embodiments of the present invention is to at least partially meet one or more needs of the prior art. According to one aspect of the present invention, there is provided a memory device comprising: at least one memory cell comprising: first and second pairs of transistors, each pair coupled in series between first and second supply voltages, a first node of storing between the transistors of the first pair of transistors being coupled to drive terminals of the second pair of transistors, and a second storage node between the transistors of the second pair of transistors being coupled to control terminals of the first pair of transistors pair of transistors; B10704 - 03914-05

3 and a first resistance switching element coupled between the first supply voltage and a first transistor of the first pair of transistors and programmed to have one of a first and a second resistor; and a control circuit adapted to store a data value at the first and second storage nodes by coupling the first storage node to the second supply voltage, the data value being determined by the programmed resistance of the first storage element. resistance switching.

According to one embodiment, the memory device further comprises a fifth transistor coupled between the first storage node and a first access line, and a sixth transistor coupled between the second storage node and a second access line coupled between the first supply voltage and a first transistor of a second pair of transistors and programmed to have one of a first and a second resistor, the data value being determined by the relative resistances of the first and second resistors .

According to another embodiment, said at least one memory cell further comprises a second resistance switching element coupled between the first supply voltage and a first transistor of the second pair of transistors and programmed to have one a first and a second resistor, the fifth transistor being controlled by a first control line and the sixth transistor being controlled by a second control line independent of the first control line. According to another embodiment, the control circuit is adapted to couple, before storing the data value at the first and second storage nodes, the first storage node to the first supply voltage, and the control circuit is adapted to store another data value at the first and second storage nodes by coupling the second node of B10704 - 03914-05

4 storing at the first power supply voltage, then coupling the second storage node to the first power supply voltage. According to another embodiment, said at least one memory cell further comprises another resistance switching element coupled between the second supply voltage and a second transistor of the first pair of transistors and programmed to have one a first and a second resistance.

According to another embodiment, the control circuit is further adapted to store another data value at the first and second storage nodes by coupling the first storage node to the first supply voltage, the data value. being determined by the programmed resistance of the other resistance switching element. In another embodiment, the control circuit is adapted to select between storing said data value and storing the other data value at the first and second storage nodes by applying the first or second supply voltage to the first and second storage nodes. first storage node. According to another embodiment, said at least one memory cell further comprises: a third resistance switching element coupled between the second supply voltage and a second transistor of the first pair of transistors and programmed to have one of a first and a second resistance; and a fourth resistance-coupled element coupled between the second supply voltage and a second transistor of the second pair of transistors and programmed to have one of the first and second resistors; and the control circuit is further adapted to store another data value at the first and second storage nodes by coupling the first storage node to the first power supply voltage. B10704 - 03914-05

the data value being determined by the relative resistances of the third and fourth resistance switching elements. According to another embodiment, the memory device further comprises a programming circuit adapted to program the resistances of the first resistance switching element based on input data. In another embodiment, the first resistance switching element is one of the following: an oxide resistive element; a conduction element; a phase change element; a programmable metallization element; a spin transfer element; a thermally-assisted switching element, and a field-induced magnetic switching element.

According to another aspect of the present invention, there is provided a random access memory comprising a network of the aforementioned memory devices. According to yet another aspect of the present invention, there is provided an on-site programmable gate array comprising at least one multiplexer comprising an input coupled to at least one of the aforementioned memory devices. According to yet another aspect of the present invention there is provided an on-site programmable gate array comprising: a plurality of configurable logic blocks; and at least one switching block adapted to interconnect the plurality of configurable logic blocks, said at least one switching block comprising the aforementioned memory device. According to another aspect of the present invention, there is provided a method for transferring a data value from a nonvolatile storage location of a memory cell to first and second volatile storage nodes of said memory cell, wherein the memory cell comprises first and second pairs of transistors, each pair being coupled in series between B10704 - 03914-05

First and second supply voltages, wherein a first storage node between the transistors of the first pair of transistors is coupled to control terminals of the second pair of transistors, and a second storage node between the transistors of the second pair of transistors; second pair of transistors is coupled to control terminals of the first pair of transistors; and a first resistance switching element coupled between the first supply voltage and a first transistor of the first pair of transistors and programmed to have one of a first and a second resistance, the method comprising the step next coupling the first storage node to the second supply voltage, the data value being determined by the programmed resistance of the first resistance switching element. BRIEF DESCRIPTION OF THE DRAWINGS The aforementioned and other objects, features, aspects and advantages of the invention will become apparent upon reading the following detailed description of embodiments, given by way of illustration and not limitation. with reference to the accompanying drawings, in which: Figure 1 (previously described) illustrates a volatile SRAM cell; Figure 2 illustrates a memory cell having nonvolatile data storage according to an embodiment of the present invention; FIG. 3 illustrates a programming circuit for programming the non-volatile portion of the memory cell of FIG. 2; Figures 4A and 4B schematically show examples of the programming of a particular resistance switching memory device; Fig. 5 is a timing chart illustrating an example of the signals used to program the nonvolatile portion of the memory cell of Fig. 3; B10704 - 03914-05

FIG. 6 illustrates an exemplary control circuit for copying data stored by nonvolatile data storage elements into volatile data storage elements of the memory cell; Figs. 7A and 7B are timing diagrams showing examples of signals in the circuit of Fig. 6; Figs. 7C and 7D are graphs illustrating the transition between stable states of the cell of Fig. 6 in one example; Fig. 8 illustrates a memory cell having nonvolatile data storage according to another embodiment of the present invention; Fig. 9 illustrates a memory cell having nonvolatile data storage according to yet another embodiment of the present invention; Fig. 10 illustrates a memory cell having nonvolatile data storage according to yet another embodiment of the present invention; Figs. 11A to 11D are graphs illustrating the transition between stable states of the cell of Fig. 10 according to some embodiments of the present invention; Fig. 12 illustrates a memory cell having nonvolatile data storage according to another embodiment of the present invention; Fig. 13 illustrates a memory array according to an embodiment of the present invention; Fig. 14A illustrates an on-site programmable gate array (FPGA) according to an embodiment of the present invention; and FIG. 14B illustrates in more detail a configurable logic block of the FPGA of FIG. 14A according to one embodiment of the present invention. In the figures, similar elements bear the same references.

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DETAILED DESCRIPTION OF THE REALISING NAME OF THIS FIGURE FIG. 2 illustrates a memory cell 200 which stores, in addition to a volatile data bit, a nonvolatile data bit. The volatile data is stored in electronic form by a flip-flop. However, the non-volatile data is stored by the physical state of a pair of resistance switching elements, as will now be described. The memory cell 200 is similar to the SRAM cell 100 of FIG. 1 previously described, and the common portions will not be described again in detail. The difference is that the memory cell 200 further comprises resistance switching elements 202 and 204, which are coupled between the respective sources of the transistors 102 and 104 and the ground voltage.

The resistance switching elements 202 and 204 may be any switchable resistive element between two resistance values. Such elements maintain the programmed resistive state even after the withdrawal of a supply voltage. The elements 202, 204 are programmed to have opposite values, and the relative resistance values of the elements indicate a binary data value. For example, the resistance switching elements 202, 204 are based on magnetic tunnel junctions (MTJ), such as field-induced magnetic switching (FIMS) elements, thermally-switched switching elements (TAS), STT elements. (spin transfer), or those of toggle MRAMs. FIMS-MRAM (magnetic random access memories) are for example described in more detail in the publication entitled "Magnetoresistive random access memory using magnetic tunnel junctions", S. Tehrani, Proceedings of IEEE, 91 (5): 3707-714, May 2003. Examples of SAR-MRAM are described in more detail in the publication entitled "Thermally Assisted MRAM", Prejbeanu et al. Alternatively, the resistance switching elements 202, 204 could be other types of resistance switching memory devices, including those used in programmable metallization cells (PMCs). ), such as oxide resistive RAM (OxRRAM), conduction RAM (CBRAM), or phase change RAM (PCRAM).

Regardless of the type of resistance switching element, the information is stored by putting one of the elements at a relatively high resistance (Rmax), and the other at a relatively low resistance (Rmin). Each of the resistance switching elements 202, 204 has for example only two resistive states corresponding to the high and low resistors Rmax and Rmin, although the exact values of Rmin and Rmax may vary depending on conditions such as temperature, variations in process, etc. The value of non-volatile data represented by the resistive elements 202, 204 depends on that of the resistive elements which is at the resistance Rmax or Rmin, in other words the relative resistances. The resistive elements 202, 204 are, for example, chosen so that Rmax is always substantially greater than Rmin, for example greater than at least 20. In general, the ratio between the resistance Rmax and the resistance Rmin is, for example, between 1, 7 and 5 for an MRAM, or more generally between 1.2 and 10000. In one example, Rmin is in the 2.5 kilo-ohm region, and Rmax is in the 5 kilo-ohm region, although many other values are possible. In operation, for reading and writing data in the volatile part of the memory cell 200, in other words in the storage nodes 106 and 108, the process is the same as for the memory cell 100 of FIG. 1, and is not affected by the programmed resistance values of the resistance switching elements 202 and 204. In short, writing a data bit in the nodes 106, 108 involves the application, while the transistors 110 and 112 are on, a high or low voltage on the bit line BL according to the data to be memorized, and the voltage B10704 - 03914-05

10 opposite on the BLB bit line. Reading the data in the nodes 106 and 108 involves pre-charging the bit lines BL and BLB, then turning on the transistors 110 and 112 and determining the voltage of the bit lines that drops first. , using a sense amplifier (not shown), which amplifies the voltage difference between the bit lines. Preferably, so as not to slow down the read and write operations in the volatile storage nodes and to prevent bit switching during a read operation, the value of Rmax is chosen so as not to be greater than about 5 kilo-ohms, although this value depends on the particular technology used, and in particular the on-state resistance of the transistors. Independently of this normal SRAM operation, the resistance switching elements can be programmed to store non-volatile data, and the memory cell can be controlled to transfer this data, from the physical storage determined by the resistive state of the elements 202. , 204, to an electronic storage determined by the voltage states of the storage nodes 106, 108. Once transferred, this data can be read in the SRAM cell in a standard manner. The programming of the resistance switching elements 202 and 204 according to one example will now be described with reference to FIGS. 3, 4A, 4B and 5. FIG. 3 illustrates the memory cell 200 accompanied by a control circuit of FIG. writing 302 arranged to program the resistance switching elements 202 and 204 based on a non-volatile data bit DNv received on an input line 304. In particular, on the basis of the nonvolatile data D1, the circuit 302 generates an IWRITE write current, which is supplied to a conductive track 306 which passes through the resistance switching elements 202 and 204. The IWRITE current flowing in the conductive track 306 generates a field B10704 - 03914-05

11 magnetic, which passes through the resistance switching elements, and programs their resistive state. In the case of a thermally-assisted switching MRAM, before supplying the write current to program each of the resistance switching elements 202, 204, the resistance switching elements are heated by passing a current thereinto , which helps the transition from one resistive state to another. According to an example illustrated in FIG. 3, a heating circuit is provided, and comprises PMOS transistors 308 and 310 coupled between the supply voltage VDD and the resistance switching elements 202, 204, respectively. Transistors 308 and 310 are activated by a "HEAT" control signal at their gate terminals to conduct currents through each resistance switching element 202, 204. Instead, or in addition, a control circuit For example, the heater 312 is provided, which applies to each of the lines BL and BLB a voltage which is for example equal to or greater than the supply voltage V DD. Then, by activating the transistors 110 and 112 by a logic high voltage on the word line WL, a current will flow from the bit lines BL and BLB through the resistance switching elements 202, 204 to the mass voltage.

FIGS. 4A and 4B show in more detail the resistance switching elements 202 and 204, in the example where they are TAS elements. Each of the resistance switching elements 202, 204 comprises a fixed ferromagnetic plate 402 and a free ferromagnetic plate 404, the plates 402 and 404 sandwiching a tunnel oxide layer 406. The conductive track 306 passes near the free plate 404 of ferromagnetic material, so that it is affected by the magnetic field generated by the current IWR TE passing in the track 306. The fixed plate 402 has for example a magnetic orientation in a first direction, while the magnetic orientation B10704 - 03914-05

12 of the plate 404 can be programmed, by the polarity of the current IWRITE, to be in the same direction or in the opposite direction with respect to the plate 402. However, programming takes place only in elements which have already been heated, as described in more detail below. FIG. 4A illustrates the case where the magnetic orientations have opposite directions in the plates 402, 404, resulting in a maximum resistance Rmax for the resistance switching element 202, for example in the range of 2 kilo-ohms to kilohms. FIG. 4B illustrates the case where the magnetic orientations have the same direction in the plates 402 and 404, resulting in a minimum resistance Rmin of the resistance switching element 204, for example in the range of 100 ohms to 3 kilograms. ohms. The conductive track 306 is arranged such that the IWRITE current passes through each resistance switching element 202, 204 in opposite directions, one of which corresponds to the magnetic orientation of the fixed plate 402, and the other corresponds at the opposite direction. Thus, the same IWRITE current can be used to program the two resistive states of the resistance switching elements 202 and 204 at the same time, one being Rmax, and the other Rmin- Figure 5 is a timing diagram illustrating an example of the HEAT signal in the case where the transistors 308, 310 are present, and the IWRITE signal during the programming of the resistance switching elements 202, 204. In the case where the circuit 312 is present in addition or instead, the signal WL is for example the inverse of the heating signal HEAT.

The HEAT signal goes low on a falling edge 502, thereby activating the transistors 308 and 310. This generates an IHEAT current in the resistance switching elements 202 and 204, and after a certain period the IWRITE signal is activated. as represented by the rising edge 504 of this signal. In the example of Figure 5, on the B10704 - 03914-05

On the rising edge 504, the current becomes positive, which, for example, programs the element 202 to be at a high resistance value Rmax, and the element 204 to be at a low resistance value Rmin. HEAT is again raised to a high state by a rising edge 506, so that the heating current IHEAT is stopped, and the resistance switching elements 202, 204 cool in their current resistive state. Then the IWRITE signal is brought down by a falling edge 508, to terminate the programming process. The following transitions of the signals of FIG. 5 correspond to the programming of opposite resistive states of the resistive elements 202, 204. These transitions are identical to those described previously, except that the IWRITE signal becomes negative by the falling edge 510, instead of positive, to program the opposite resistive states. In one example, the time during which the HEAT signal is active between the edges 502 and 506 is about 20 ns.

Thus, a write operation can be performed in just under 35 ns. However, the heating and cooling times will vary depending on such factors as the materials used, their volume, etc., and also heating currents that are applied, and thus the above-mentioned values are given only as rough example. The IWRITE current is for example in the 10 mA region for programming a value of the data bit, or in the -10 mA region for programming the opposite value of the data bit, although other values may be used.

Figure 6 illustrates the memory cell 200 with a transfer control circuit 602 for controlling the transfer of data stored in the nonvolatile portion of the memory cell to the volatile data storage portion. In particular, the circuit 602 includes output lines 604 and 606, coupled to the bit lines BL and BLB B10704-03914-05

14 respectively, and an output line 608 coupled to the word line WL. The signals on the word line WL and the bit lines BL and BLB during a non-volatile to volatile storage transfer phase will be described with reference to FIGS. 7A and 7B. In general, the transfer phase comprises the application, by the control circuit 602, of a supply voltage to each of the storage nodes 106, 108, via the bit lines BL and BLB and the transistors NMOS 110, 112. In particular, the supply voltage VDD is applied to the bit lines BL and BLB, while the signal of the word line WL is in the high state, thereby activating the transistors 110 and 112. has the effect of putting the transistors 103, 105 in the on state, and activating them to generate a current in the resistor 202, 204. One on each side of the memory cell, and the voltages on the nodes 106, 108 will depend on the relative resistances of the elements 202, 204. Figs. 7A and 7B show timing diagrams illustrating the voltages on the bit lines BL and BLB, as well as on the word line WL, and the corresponding voltages Q and Q on the nodes 106 and 108.

Initially, the circuit 602 applies a high voltage to each of the bit lines BL, BLB, for example equal to the supply voltage VDD. The bit lines BL and BLB are likely to be close to or equal to the supply voltage VDD during a waiting or reading phase before the transfer phase, but during such phases they are usually only periodically charged to the supply voltage, and for this reason, the BL and BLB voltages before and after the transfer phase have been indicated by dashed lines in FIGS. 7A and 7B. On the contrary, during the transfer phase, the voltage of the power supply transistors 102 and 104, and thus each of the voltage divider switching elements is thus formed B10704 - 03914-05

15 is applied constantly to the bit lines BL, BLB, as indicated by the solid lines in FIGS. 7A and 7B, so that currents can be drawn from the bit lines.

Then, the voltage of the word line WL is raised to turn on the transistors 110 and 112. Figure 7A assumes that the SRAM cell is initially in a state in which Q is low and Q is high. Thus, initially, the transistor 104 will be non-conductive and the transistor 102 conductive. However, it is also assumed that the resistance switching element 202 has a resistance Rmax, and thus the current flowing through it will be limited. This current causes the voltage Q to rise towards VDD, which causes the activation of the transistor 104, causing a second current to flow in the resistor 204, which has a low resistance Rmin. This will also reduce the voltage to 0 V. The NMOS transistors 110, 112 are chosen to have equal dimensions and thus very similar resistances to the off state, so that the voltage drop in each transistor 110, 112 will be proportional to the level of current passing through them. Thus, the lower voltage drop in the transistor 110 will cause a higher voltage Q on the node 106. Therefore, because of the difference between the resistors of the resistive elements 202 and 204, the equilibrium position will be such that the voltage Q on the node 106 will be closer to VDD, and the voltage é on the node 108 will be closer to 0 V. Then, the voltage of the word line goes to the low state, which isolates the storage nodes 106, 108 of the bit lines BL and BLB, and the states of Q and Q will settle to the nearest stable state. In particular, because of the voltage difference, even if it is small, between the Q and Q voltages, the storage nodes 106, 108 will be set to a state in which Q is high and Q is low, which corresponds to in the state memorized by the elements 202 and 204.

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FIG. 7B illustrates the case in which Q and Q are again initially equal to 0 V and VDD respectively, but in which the element 202 is at Rmin, and the element 204 at Rmax-In this case, the transistor 102 will again initially be conductive, and the transistor 104 non-conductive, but again the voltage on the node 106 will rise due to the current flowing in the resistance switching element 202. However, when the current in the element 204 begins to mount, this will be a low current due to the high resistance of the element 204, and so the voltage Q will remain relatively high, and the voltage Q relatively low. Then, when the voltage of the word line WL is again brought to the low state, which isolates the storage nodes 106, 108 from the respective bit lines, the states of the storage nodes 106, 108 will return to their respective state. set to their original states, where Q is low and Q is high. In both FIGS. 7A and 7B, the duration during which the supply voltage is applied to the bit lines BL and BLB is, for example, in the region of 1 ns, and thus such a data transfer of the nonvolatile storage to the volatile storage can be achieved in about 1 ns only, a time comparable to the read and write times of the SRAM portion of the memory cell 200. Figures 7C and 7D are graphs illustrating the transitions between different states of Q and Q. Figure 7C illustrates the case of a transition to a high Q state, Q low. Starting from the low Q state, Q high noted 702, when Q begins to rise, we will follow the curve 704, on which Q initially drops slowly until reaching a bend 706 and the transistor 104 begins to become conductive. Then goes down faster than Q goes up and we pass a point of metastability 707, for which the points Q and Q are equal. Q will then reach a voltage Vmax at a point 708, resulting in a relatively large voltage drop across resistor Rmax and transistor 102. From this point 708, B10704 - 03914-05

The closest steady state is the high Q state, Q low. Thus, when the signal WL is brought to the low state, the state Q up, é low, noted 710, will be reached, è rapidly descending to the logic state 0, shortly before Q reaches the state As an alternative, if one starts from the high Q state, Q low 710, one will follow a curve 712 of FIG. 7C, in which Q will initially descend very slowly while Q goes up, until reaching an elbow 714 when the transistor 102 begins to become conductive. Q then descends more rapidly to a point 716 when Q is at Vmin, which results from the relatively low voltage drop in the resistor Rmin and the transistor 104. In this example, the metastability point 707 has not been passed, and from this point 716, the closest steady state returns to the high Q, low Q state. Thus, when the signal WL is brought to the low state, Q will quickly return to the logic state 1, before Q drops back to the logic state O. In FIG. 7D, the same curves are shown in FIG. in Figure 7C, but for transitions to a low Q state, Q high, corresponding to an opposite magnetic state of the elements 202, 204 with respect to the example of Figure 7C. Thus, the point Vmax 720 and the point Vmin 722 are both closest to the low Q state, Q high.

As shown by the curves of FIGS. 7C and 7D, regardless of the initial states of the Q and Q voltages, the new states of these voltages will be determined by the programmed resistance values of the elements 202 and 204. In particular, the elements 202 and 204 are in an intermediate state 708, 716, 720 or 722, in which the values of Q and Q are the closest to the steady state corresponding to the programmed states of the elements 202, 204. In variant embodiments of Figure 2, the element 202 or 204 could be replaced by a resistor B10704 - 03914-05

18 having a fixed resistance between Rmin and Rmax, for example equal to Rmin + (Rmax-Rmin) / 2. FIG. 8 illustrates a memory cell 800, which is the same as the memory cell 200 of FIG. 2, except that the resistance switching elements, denoted 202 'and 204' in FIG. 8, are respectively coupled between the transistors 103, 105 and the supply voltage VDD, and thus the transistors 102, 104 are coupled directly to ground. Circuit 800 operates similarly to circuit 200. However, circuit 312 of FIG. 3 will apply a low voltage on the bit lines to heat resistance switching elements 202 ', 204'. In addition, in the circuit 800, the heating transistors 308, 310 of FIG. 3 could be implemented by NMOS transistors coupled between the elements 202 ', 204' and the ground voltage. In addition, a low supply voltage, for example 0 V, will be applied by the circuit 602 of FIG. 6 to the bit lines BL and BLB during the transfer phase of the nonvolatile storage elements 202 ', 204' to the volatile storage nodes 106, 108. This will have the effect of activating the transistors 103 and 105, and deactivating the transistors 102 and 104, so that the currents passing through the elements 202 ', 204' will depend on the resistances programmed from these elements, thereby establishing the voltage states of the nodes 106 and 108. FIG. 9 illustrates a memory cell 900, which is the same as the memory cell 800 of FIG. 8, except that it further comprises a pair of resistance switching elements 202, 204 coupled between transistors 102, 104, respectively, and ground. Each pair of elements 202, 204 and 202 ', 204' is programmed to store an independent bit of nonvolatile data, and either of these bits can be transferred to the storage node 106, 108, as we will describe it in more detail below.

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To program the elements 202, 204, they are, for example, heated by the heating circuit 308, 310 and / or the heating control circuit 312 of FIG. 3, before being programmed by the write control circuit. In order to program the elements 202 ', 204', they are for example heated by transistors similar to the transistors 308 and 310 of FIG. 3, but coupled to ground, and / or by applying a low voltage on the bit lines. BL and BLB by the heater control circuit 312.

A transfer control circuit 902 controls the transfer of non-volatile data to the storage nodes 106, 108. The circuit 902 has output lines 904 and 906 coupled to the bit lines BL and BLB respectively, and an output line 908 coupled to the word line WL. It receives on an input line 910 a selection signal Sj1,2, which indicates whether the bit memorized by the elements 202, 204 or by the elements 202 ', 204' must be transferred. On the basis of this selection, the circuit 902 applies to the bit lines BL and BLB a high voltage level, for example equal to VDD, to transfer the data bit stored by the elements 202, 204, ie a voltage level. low, for example to ground, to transfer the data bit stored by the elements 202 ', 204'. Then, the circuit 902 activates the word line signal WL to activate the transistors 110 and 112, and depending on the voltage level on the bit lines BL and BLB, the voltage states on the nodes 106 and 108 will depend on the programmed resistances of elements 202, 204 or elements 202 ', 204'. FIG. 10 illustrates a memory cell 1000 according to another embodiment, which is identical to the memory cell 200 of FIG. 2, but in which the resistance switching elements 202, 204 are independently programmed to have one of the two states of resistance Rmin and Rmax. Thus, each element 202, 204 can independently store a nonvolatile data bit. In addition, rather than having a single WL word line, two word lines were provided B10704 - 03914-05

WL1 and WL2, WL1 being coupled to the gate of transistor 110, and WL2 to the gate of transistor 112. These two word lines allow selection of the non-volatile data bit stored by element 202 or element 204 to be transferred to the volatile storage nodes 106, 108, as described below. In order to program the resistance of each of the elements 202, 204, they are for example heated as has been described previously with reference to FIG. 3, and a write control block, such as the block 302 of FIG. example provided for each element, which allows to apply independent write currents to program each element. A transfer control circuit 1002 is coupled via lines 1004 and 1006 to the BL and BLB bit lines respectively, and via lines 1008 and 1010, to the word lines WL1 and WL2 respectively. A selection signal SNV1,2 on an input line 1012 of the circuit 1002 indicates whether the non-volatile data bit stored by the element 202 or the element 204 must be transferred to the volatile storage nodes 106, 108 Such a transfer will now be described with reference to Figs. 11A-11D. Figs. 11A and 11B are graphs illustrating the state of the storage node 108 during a transfer phase.

Initially, the storage node connected to the element 202 or 204 to be read, as indicated by the selection signal 5r1, 2, is set to a low value. In the example of Figs. 11A and 11B, the element 204 is to be read, and thus a low logic level is applied to the storage node 108, and a logic high level to the storage node 106. For example, this is achieved by performing a write operation, which programs a logic state 1 on the node 106 and a logic state 0 on the node 108. Thus, in both FIGS. 11A and 11B, the initial state 1102 corresponds to the low Q state, Q high.

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The transfer control circuit 1002 then applies a high voltage to the word line WL2 to turn on the transistor 112 while maintaining a low voltage on the word line WL1. The supply voltage level is also applied by the circuit 1002 to the bit line BLB. This causes a current flow of the bit line BLB, through the transistors 112, 104 and the resistance switching element 204, to ground. Thus, the transistors 112, 104 and the element 204 form a potential divider, and the voltage on the node 108 will depend on the programmed resistance of the element 204. In the case of Fig. 11A, the resistance of the element 204 is Rmin, and thus the voltage on node 108 descends along a curve 1104 and passes a meta-stability point 1106, before reaching a point 1108 where e is at a level Vmin resulting from the resistance Rmin. Thus, when the circuit 1002 causes the voltage on the word line WL2 to go low again to turn the transistor 112 off, the storage nodes 106 and 108 go to the nearest stable state, which is the Q low, Q high. In the case of FIG. 11B, the resistance of the element 204 is at Rmax, and thus the voltage on the node 108 goes down along a curve 1104 but does not pass the metastability point 1106. Instead, it stops at a point 1110, for which is at a level Vmax resulting from the resistance Rmax. Then, when the circuit 1002 causes the voltage on the word line WL2 to go low again to turn the transistor 112 off, the storage nodes 106 and 108 go to the nearest stable state, which is the same. Q high, Q low. FIGS. 11C and 11D both illustrate the curve 1104 described above, corresponding to a reading of the non-volatile data bit stored by the element 204, and also a curve 1112 corresponding to the reading of the non-volatile data bit memorized by the element 202. For curve 1112, state B10704 - 03914-05

22 is the state Q high, Q low, referenced 1114. If the element 202 is Rmax, the voltage on the node 106 will go down along the curve 1112 to a point 1116, for which Q is at a voltage Vmax, without passing the metastability point 1106. From point 1116, the closest steady state is the high Q state, Q low. Alternatively, if the element 202 is at Rmin, the voltage on the node 106 will go down the curve 1112 beyond the metastability point 1106 to a point 1118, and thus the most stable state. near is the low Q state, Q high. The values of the resistors Rmin and Rmax of the elements 202 and 204 are for example chosen such that, when the supply voltage is applied to the corresponding bit line BL, BLB, the corresponding voltages Vmin and Vmax satisfy the relationship Vmin < Vmet <Vmax, where Vmet is the voltage on the nodes 106 and 108 corresponding to the metastability point 1106 of the SRAM portion of the memory cell. In an alternative embodiment with respect to FIG. 10, one or the other of the elements 202, 204 could be removed, resulting in a simpler structure storing a volatile data bit and a non-volatile data bit. In this case, rather than having two word lines WL1, WL2, we could use only one word line. As a variant, while keeping the two word lines WL1, WL2, it would be possible to perform a read or write operation on only the branch having no resistance switching element, selectively activating the transistor 110, 112 corresponding during this operation. This leads to a faster read or write operation. In addition, in such a case, a higher resistance can be used for the element 202/204, for example having a maximum resistance Rmax greater than 5 kilo-ohms. Thus, it will be less likely to have a bit switch during a read operation. Figure 12 illustrates a memory cell 1200 according to yet another embodiment, which is the same as the B10704 - 03914-05 mode.

23, but which further comprises a pair of resistance switching elements 202 ', 204' coupled between the transistors 103 and 105 respectively and the supply voltage VDD. The elements 202 and 204 are independently programmed to store two nonvolatile data bits, while the elements 202 'and 204' are programmed to have different resistances Rmin 'Rmax, and thus together store a nonvolatile data bit. Thus, the memory cell 1200 can store a volatile data bit on the nodes 106 and 108, and three bits of non-volatile data. The operation of the memory cell 1200 is identical to that of the memory cell 1000 of FIG. 10, except that the transfer control circuit 1002 is replaced by a circuit 1202, which is furthermore designed to transfer the data stored by the elements 202 'and 204' to the storage nodes 106, 108 by applying low voltages on the bit lines BL and BLB, then activating the transistors 110 and 112. The circuit 1202 receives a selection input SNV1,2,3 on a line 1212 indicating which bit of nonvolatile data is to be transferred to the nodes 106, 108. In addition, the embodiment of Fig. 12 could be extended to store four nonvolatile data bits, independently programming the switching elements. in this case, the circuit 1202 is further arranged to transfer the data stored by one or the other of the elements 202 or 204 to the nodes of the same. Morisation 106, 108 using the same technique as that described in connection with Figure 10, except that a low voltage will be coupled to the corresponding bit line, while the corresponding transistor 110, 112 is activated. The circuit 1202 will also receive a selection input SNV1,2,3,4 on a line 1212 indicating which of the four nonvolatile data bits is to be transferred to the nodes 106, 108. In a B10704 - 03914-05

In such an embodiment, in order to compensate for the different resistances in the conducting state of the various transistors 102 to 105, the minimum resistance Rmin of the elements 202 ', 204' is for example chosen to be less than the minimum resistance Rmin of the elements 202. 204, and the maximum resistance Rmax of the elements 202 ', 204' is for example chosen to be less than the maximum resistance Rmax of the elements 202, 204. For example, for the elements 202, 204, Rmin could be equal to 2, 5 kilo-ohms and Rmax could be equal to 5 kilo-ohms, while for elements 202 'and 204', Rmin could be equal to 1.5 kilo-ohms and Rmax could be equal to 3 kilo-ohms. For example, in the case where the elements 202, 204, 202 'and 204' are implemented by magnetic tunnel junctions, this could be obtained by choosing a diameter of 120 nm for the elements 202 and 204 and a diameter of 140 nm for the elements 202 'and 204'. FIG. 13 illustrates a memory array 1300 of the memory cells 200, although the memory cell 200 can be replaced by any of the memory cells 800, 900, 1000 or 1200 described previously. The memory cells 200 are arranged in columns and in rows, each cell being coupled to bit lines BL and BLB common to each of the columns. The bit lines are coupled to a control circuit 1302, which for example receives DVIN volatile input data, and provides volatile output data DVOUT, which could be volatile data input from outside, or volatile data. which are generated by a transfer of the nonvolatile data stored by the resistance switching elements. The circuit 1302 also controls, for example, the voltages on the bit lines BL and BLB during the transfer phase, and, if appropriate, during the writing of the nonvolatile data. Each of the memory cells 200 is also coupled to a corresponding word line WL common to each row of cells, although obviously, if the memory cells B10704 - 03914-05

25 are those of Figures 10 or 12, two such wordlines will be provided at each row. A conductive track 306 forms a loop through each cell and conducts IWRITE current to write to the resistance switching elements of each of the memory cells. In embodiments in which the cell stores more than one bit of nonvolatile data, one could provide for example several conductive tracks 306, one for each independently programmable element or pair of elements.

Each of the lines WL and 306 is controlled by a control circuit 904, which receives as input one or more non-volatile data bits DNvin, and supplies the IWRITE current of the corresponding polarity on one or more tracks.

The writing of the non-volatile data is for example carried out row by row, in two phases. During a first phase, only the resistance switching elements of the cells for which a first logic value, such as the logic value "0", must be programmed, are heated.

Then, when the corresponding write current is applied to said one or more conductive tracks 306, the resistive states of the only elements that have been heated will be programmed. During the second phase, the resistance switching elements of the other cells, for which the second logic value, for example a logic value "1", must be programmed, are heated. Thus, when the corresponding write current is applied to said one or more conductive tracks 306, here again only the resistive states of the elements that have been heated will be programmed.

As indicated by dashed lines in FIG. 13, the memory array 1300 may comprise any number of cell rows and any number of cell columns, depending on the desired storage capacity.

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The example of FIG. 13, in which a common track 306 is used for each row of memory cells, has the advantage of being efficient in terms of energy consumption. Indeed, it is possible to use a single current on each track 306 to program several memory cells of the row. Alternatively, a common track 306 could be used for each column, which has the advantage that a row of memory cells can be fully programmed in a single programming cycle. In addition, since a current generator supplies the current on each track 306, the number of current generators could then be reduced to the number of columns rather than the number of rows of the memory.

Figure 14A illustrates an on-site programmable gate array 1400 in which the memory cells 200, 800, 900, 1000 or 1200 described herein can be implemented. The FPGA comprises a network of configurable logic blocks (CLBs) 1402 selectively interconnected by line columns 1404, which in turn are selectively interconnected with rows of lines 1406. In particular, switching blocks 1408 are provided at each intersection between the rows of columns 1404 and row lines 1406, making it possible to program the connections between each of the rows of columns 1404 and each of the rows of rows 1406. The switching blocks 1408 comprise, for example, one or more of the memory cells 200, 800, 900, 1000 or 1200, to program the connections between the lines in a non-volatile way. In addition, in the case where the memory cells 900, 1000 or 1200 are used to program the connections, one of a plurality of connection configurations can be selected by selecting the nonvolatile data bits which are transferred to the nodes. memorizing 106, 108 of each cell.

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FIG. 14B illustrates in greater detail one of the CLBs 1402, according to an example in which it comprises a correspondence table formed of a multiplexer 1410 comprising 8 data inputs, each of which is coupled to a memory cell 200, although in alternative embodiments, the memory cell 200 may be replaced by the memory cell 800, 900, 1000 or 1200 described above, and there could be any number of such cells and inputs to the multiplexer. The cell 200 provides a data value from its volatile storage, that is to say from one of the storage nodes 106, 108. In this implementation, the memory cells are not coupled to the storage lines. bit of a memory network, but to access lines, which could be bit lines, or lines coupled to only one memory cell. One of these access lines for example provides the output data value of the cell. The multiplexer 1410 also includes a 3-bit control input 1412, controlling the selection of one of the 8 input lines, and an output line 1414, providing the data of the selected input line. An advantage of the embodiments of the memory cell described herein is that it is capable of storing not only a volatile data bit, but also a nonvolatile data bit. In addition, the programmed non-volatile data can be quickly loaded into the volatile part of the memory cell in a simple manner, by applying a voltage to the access lines of the memory cell. This advantageously means that a non-volatile programmed state can be loaded quickly (in less than 1 ns), for example when the memory is activated at the time of power up or after a standby period. In the case of an FPGA, this makes it possible to quickly initiate a circuit design, without the need to load external data into the device to program memory flip-flops and switches.

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In addition, advantageously, the cell is capable of fast write and read operations (about 1 ns) for the volatile storage portions, which can occur in a normal manner without taking into account the programmed states of the nonvolatile resistive elements. In addition, the write time for the non-volatile portion is also relatively fast (about 35 ns in the case of an MRAM). Another advantage of the memory cells described herein is that the nonvolatile data can be read without the need for additional transistors in each memory cell. In addition, the resistance switching elements 202, 204 of FIGS. 2, 8, 9, 10 and 12 are for example formed in a metal layer above a silicon layer in which the transistors 102, 103, 104 and 105 are formed. The positioning of these resistance switching elements 202, 204 connected directly to the ground voltage or to the supply voltage VDD is thus advantageous since only one via going from the silicon layer to a terminal of each element can be used. resistance switching, and the other terminal of each element can be connected directly to the corresponding power rail rather than return to another via to the silicon layer. An advantage of the embodiments of FIGS. 9, 10 and 12 is that several nonvolatile data bits can be stored in a single memory cell and accessed selectively by transferring the selected bit to the volatile storage. With the description thus made of at least one illustrative embodiment of the invention, various variants, modifications and improvements will be apparent to those skilled in the art. For example, it will be clear to those skilled in the art that although the invention has been described in relation to a memory array and an FPGA, the memory cell described herein could be B10704-03914-05.

29 used in other types of memory devices, such as registers or latches. It will be clear to those skilled in the art that the ground voltage described herein may be at OV, or more generally at any VSS supply voltage, which could be different from 0 V. In addition, it will be clear for Those skilled in the art that the various transistors described herein could be implemented by NMOS or PMOS devices. For example, rather than being implemented by NMOS transistors, the transistors 110, 112 could be implemented by PMOS transistors. Also, although the various embodiments have been described in connection with MOS transistors, it will be clear to those skilled in the art that the invention could also be applied to other transistor technologies, such as bipolar transistors. . In addition, the features described in connection with the various embodiments could be combined in any way in alternative embodiments.

Claims (15)

REVENDICATIONS1. Memory device comprising: - at least one memory cell comprising: first and second pairs of transistors, each pair coupled in series between first and second supply voltages (VDD, GND), a first storage node between the transistors of the first pair of transistors being coupled to drive terminals of the second pair of transistors, and a second storage node between the transistors of the second pair of transistors being coupled to control terminals of the first pair of transistors; and a first resistance switching element (202) coupled between the first supply voltage (VDD, GND) and a first transistor of the first pair of transistors and programmed to have one of a first and a second resistance; and a control circuit (602, 902, 1002, 1202) adapted to store a data value (D1) at the first and second storage nodes by coupling the first storage node to the second power supply voltage (VDD). , GND), the data value being determined by the programmed resistance of the first resistance switching element. The memory device according to claim 1, further comprising a fifth transistor (110) coupled between the first storage node and a first access line (BL), and a sixth transistor (112) coupled between the second storage node and a second access line (BLB), said control circuit being arranged to couple the first storage node to the second supply voltage by activating the first transistor. Memory device according to claim 1 or 2, wherein at least one memory cell further comprises a second resistance switching element (204) coupled between the first power supply voltage (VDD, GND) and a first power supply element (B10704-03914). A transistor of a second pair of transistors and programmed to have one of a first and a second resistor, the data value being determined by the relative resistances of the first and second resistors. The memory device according to claim 2, wherein said at least one memory cell further comprises a second resistance switching element (204) coupled between the first power supply voltage (VDD, GND) and a first transistor of the second pair of transistors and programmed to have one of a first and a second resistor, the fifth transistor being controlled by a first control line (WL1) and the sixth transistor being controlled by a second control line (WL2) independent of the first command line. The memory device according to claim 4, wherein the control circuit is adapted to couple, before storing the data value at the first and second storage nodes, the first storage node to the first power supply voltage. and wherein the control circuit is adapted to store another data value at the first and second storage nodes by coupling the second storage node to the first supply voltage and then coupling the second storage node to the first storage node. first supply voltage. The memory device according to any one of claims 1 to 5, wherein said at least one memory cell further comprises another resistance switching element (202, 204) coupled between the second power supply voltage and a second transistor of the first pair of transistors and programmed to have one of a first and a second resistance. The memory device according to claim 6, wherein the control circuit is further adapted to store another data value (DNV2) at the first and second storage nodes by coupling the first memory node. at the first supply voltage, the data value being determined by the programmed resistance of the other resistance switching element. The memory device according to claim 7, wherein the control circuit is adapted to select between storing said data value and storing the other data value at the first and second storage nodes by applying the first or second voltage. supply to the first storage node. The memory device according to any one of claims 1 to 8, wherein: said at least one memory cell further comprises: a third resistance switching element (202, 204) coupled between the second power supply voltage and a second transistor of the first pair of transistors and programmed to have one of a first and a second resistor; and a fourth resistance switching element (202, 204) coupled between the second supply voltage and a second transistor of the second pair of transistors and programmed to have one of the first and second resistors; and - the control circuit is further adapted to store another data value (DNV2) at the first and second storage nodes by coupling the first storage node to the first supply voltage, the data value being determined by the relative resistances of the third and fourth resistance switching elements. The memory device according to any of claims 1 to 9, further comprising a programming circuit (302) adapted to program the resistances of the first resistance switching element based on input data (Dy) .B10704 - 03914-05 33 The memory device according to any one of claims 1 to 10, wherein the first resistance switching element is one of the following: an oxide resistive element; a conduction element; a phase change element; a programmable metallization element; a spin transfer element; a thermally-assisted switching element (TAS), and a field-induced magnetic switching element (FIMS). A random access memory comprising a network of memory devices according to claims 1 to 11. 13. A programmable on-site gate network comprising at least one multiplexer comprising an input coupled to at least one of the memory devices of claims 1 to 11. An on-site programmable gate array comprising: a plurality of configurable logic blocks (CLBs); and at least one switching block (1008) adapted to interconnect the plurality of configurable logic blocks, said at least one switching block comprising the memory device of any one of claims 1 to 11. A method for transferring a data value (DNv) from a nonvolatile storage location of a memory cell to first and second volatile storage nodes of said memory cell, wherein the memory cell comprises first and second pairs of transistors, each pair being coupled in series between first and second supply voltages (VDD, GND), wherein a first storage node between the transistors of the first pair of transistors is coupled to terminals of the first pair of transistors. controlling the second pair of transistors, and a second storage node between the transistors of the second pair of transistors is coupled to control terminals of the first pair of transistors; and a first resistance switching element (202) coupled between the first supply voltage (VDD, GND) and a first transistor of the first pair of transistors and programmed to have one of a first and a second resistors, the method comprising the step of: coupling the first storage node to the second supply voltage (VDD, GND), the data value being determined by the programmed resistance of the first resistance switching element.