FR3035998A1 - NON-VOLATILE MEMORY WITH PROGRAMMING CIRCUIT - Google Patents

Abstract

The invention relates to a non-volatile memory comprising: a first resistive element having a first and a second node; a programming circuit (302, 304) for programming the first resistive element to take one of a first and a second resistive state (LRS, HRS), the programming circuit comprising: - a first current mirror ( 306, 312) coupled to a first supply voltage rail (VDDH) and having a first leg (312) coupled to the first node of the resistive element, and a second leg (306) coupled to a first power source ( 310); and - a first transistor (326) coupling the second node of the first resistive element to a second power supply rail (GND).

Description

B13587 - DD15341ST 1 NONVOLATILE MEMORY HAVING A PROGRAMMING CIRCUIT Domain The present description relates to the field of non-volatile memories, and in particular a nonvolatile memory comprising one or more resistive elements, and a method for programming it. PRIOR ART Non-volatile memories having programmable resistive elements have already been proposed. Such resistive elements are programmable to take one of two resistive states, a high state and a low state. The programmed resistive state is maintained even when a supply voltage of the memory is disconnected, and therefore with such elements it is possible to store data in a non-volatile manner. It would be desirable to implement such nonvolatile memory using the latest transistor technologies. However, one difficulty is that in order to program the resistive state of each resistive element, relatively high voltage levels are generally used. In addition, the use of certain types of resistive elements 20 may involve an initial forming operation, also called break-in, in which an even higher voltage level is applied across the earth. resistor element 3035998 B13587 - DD15341ST 2. Such programming and / or training voltage levels may exceed the limits of transistor technology. There is therefore a need in the art for a compact and energy efficient programming circuit for applying relatively high voltages to one or more resistive elements without exceeding the voltage limits of the transistor technology. SUMMARY An object of the present disclosure is to at least partially solve one or more needs of the interior art. According to one aspect, there is provided a non-volatile memory comprising: a first resistive element comprising a first and a second node; a programming circuit for programming the first resistive element to take one of a first and a second resistive state, the programming circuit comprising: - a first current mirror coupled to a first supply voltage rail and having a first branch coupled to the first node of the resistive element, and a second branch coupled to a first current source; and a first transistor coupling the second node of the first resistive element to a second supply voltage rail.

According to one embodiment, the programming circuit further comprises: a second current mirror coupled to the first supply voltage rail and having a third branch coupled to the second node of the first resistive element or to the first node of a second resistive element, and a second branch coupled to a second current source; and a second transistor coupling the first node of the first resistive element to the second supply voltage rail. According to one embodiment, the nonvolatile memory 35 further comprises a control circuit adapted to activate, on the basis of a data bit to be memorized by the first resistive element, the first current source and the first transistor or the second current source and the second transistor. According to one embodiment, the non-volatile memory 5 further comprises a third transistor coupled between the first or the second node of the first resistive element and an output line of the non-volatile memory. According to one embodiment, the nonvolatile memory further comprises a second resistive element having a first and a second node, the second node of the second resistive element being coupled to the second node of the first resistive element. According to one embodiment, the non-volatile memory further comprises a fourth transistor coupled between the second node of the first and second resistive elements and the second supply voltage rail, and a control circuit adapted to activate the fourth transistor while an operation of forming the first and second resistive elements.

According to one embodiment, the first branch of the first current mirror is coupled to the first node of the resistive element by means of a fifth transistor controlled at its control node by an intermediate voltage level between them. voltages of the first and second supply voltage rails. According to another aspect, there is provided a memory device comprising: a first non-volatile memory circuit comprising the aforementioned non-volatile memory; and a volatile memory comprising a first latch 30 comprising first and second inverters cross-coupled between first and second storage nodes, the first or second node of the first resistive element of the first non-volatile memory circuit being coupled to a supply voltage node of the first inverter. According to one embodiment, the memory device further comprises a second nonvolatile memory circuit comprising the aforementioned nonvolatile memory, the first or the second node of the first resistive element of the second nonvolatile memory circuit being coupled to a supply voltage node of the second inverter. According to one embodiment, the first or second node of the second resistive element of the first nonvolatile memory circuit is coupled to a voltage supply node of the second inverter. According to one embodiment, the volatile memory is a flip-flop, the first latching flip-flop being a master latch or slave latch flip-flop of the flip-flop.

According to another aspect, there is provided a nonvolatile data storage method comprising: applying by a programming circuit a voltage to a first node of a first resistive element, the programming circuit comprising a current mirror having a first branch coupled to the first node and a second branch coupled to a first current source, the voltage being applied by activating the first current source; and coupling, by a first transistor, a second node of the first resistive element to a second supply voltage rail.

BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other features and advantages will be apparent from the following detailed description of embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings in which: FIGS. 1A and 1B schematically illustrate a programmable resistive element according to an exemplary embodiment; FIG. 2 schematically illustrates a memory device provided with nonvolatile data storage according to an embodiment of the present disclosure; FIG. 3 schematically illustrates a nonvolatile memory of the device of FIG. 2 in more detail according to an embodiment of the present description; FIG. 4 schematically illustrates a flip-flop 5 comprising a nonvolatile storage of data according to an exemplary embodiment of the present description; FIG. 5 diagrammatically illustrates a control block of the flip-flop of FIG. 4 in more detail according to an exemplary embodiment; Figure 6 schematically illustrates a slave latch of the flip-flop of Figure 4 in more detail according to one embodiment; Fig. 7 is a timing chart showing an exemplary signal in the flip-flop of Fig. 4 according to an exemplary embodiment; Figure 8 schematically illustrates a nonvolatile memory of the memory device of Figure 2 in more detail according to another embodiment of the present invention; and Figure 9 schematically illustrates a nonvolatile memory of the memory device of Figure 2 in more detail according to yet another embodiment of the present description. Detailed Description In the following description, the term "connected" is used to refer to a direct connection between one element and another, while the term "coupled" implies that the connection between the two elements may be direct, or may be via an intermediate element, such as a transistor, resistor or other component. The term "approximately" is used to denote a range of plus or minus 10% around the value in question. Embodiments primarily based on resistive elements that utilize a resistance switching technology known in the art as "OxRAM" are described herein. This technology is for example described more in detail in the publication of H.S.P. Wong et al. entitled "Metal-Oxide RRAM" Proceedings of the IEEE Vol. 100, No.6, pp. 1951-1970, 2012, the content of which is considered included here within the limits authorized by law. The OxRAM elements have the characteristic of providing a relatively fast reversible switching of a transition metal oxide layer between a high resistance state (HRS) and a low resistance state (LRS). However, it will be apparent to those skilled in the art that the techniques and circuits described herein could be applied to resistive elements that utilize a wide range of technologies enabling them to be programmable to take a high or low resistive state based on the polarity of a voltage and / or the direction of a current, applied to each element. For example, the resistive elements could be based on one or more of the following technologies: CBRAM (conductive bridging RAM), as described, for example, in the publication of I.Valov, R. Waser, JR Jameson and MN Kozicki entitled "Electrochemical Metallization Memories-Fundamentals, Applications, Prospects", Nanotechnology, Vol. 22, no. 25, 254003, 2011, the contents of which are included here to the extent permitted by law; and spin transfer torque (STT) elements having anisotropy in the plane or perpendicular to the plane, as described in more detail in the publication entitled "Magnonic spin-transfer torque MRAM with low power, high speed," error-free switching ", N. Mojumder et al., IEDM Tech. Digest (2010), and in the publication "Electric toggling of magnets", E. Tsymbal, Natural Materials Vol. 11, January 2012, 30 whose content is considered included here within the limits allowed by law. FIGS. 1A and 1B schematically illustrate a programmable resistive element 100 having connection nodes 102 and 104. Element 100 is for example an element OxRAM, or a resistive element of a different type, such as has been described previously. FIG. 1A illustrates a programming phase in which a positive or negative voltage level is applied across the resistive element 100 to program either a low resistive state or a high resistive state. For example, a positive voltage is applied by coupling the node 102 to a supply voltage rail VDDH (not shown in FIG. 1A), which is for example at a voltage level VSTORE and coupling the node 104 to the ground . Such a positive voltage level for example puts the element 100 in the low resistive state (LRS) by creating a conduction path in the dielectric layer of the element 100. In the other case, a negative voltage is for example applied by coupling the node 104 to the supply voltage rail VDDH (not shown in FIG. 1A), which is again for example at a voltage level V STORE, and coupling the node 102 to ground. Such a negative voltage level resets, for example, the element 100 in the high resistive state (HRS).

Depending on the technology of the resistive element 100, and the duration during which the voltage is applied, the voltage level VsToRE which is applied to establish or reset the resistive state of the element 100 is for example between 1 and 3 V. In the case of an OxRAM element, the voltage is for example between 1 and 2 V, as approximately 1.8 V. In addition, depending on the technology of the resistive element 100, a The initial forming operation may be performed to form a conductive channel in the dielectric layer (not shown in FIGS. 1A and 13) of the resistive element. During such a forming operation, the voltage on the supply rail VDDH is for example increased to a level VFoRm between 2.2 and 2.8 V, for example about 2.5 V.

FIG. 1B illustrates a reading phase of the element 100, in which a reading voltage VREAD is applied across the element 100, the node 102 being for example coupled to the reading voltage, and the node 104 being coupled to ground. As will be described in more detail below, while the VREAD reading voltage is applied, the current in the element 100 is for example detected to detect the programmed resistive state of the element 100. In some modes Embodiments described in more detail below, two resistive elements are programmed in a complementary manner, with opposite resistive states, to facilitate the read operation. FIG. 2 schematically illustrates a memory device 200 comprising a volatile memory (VM) 202, and a non-volatile memory (NVM) 204. The volatile memory 202 is for example a flip-flop, a latch, or other type of device storing a data bit in a volatile manner. The volatile memory 202 receives, for example, DIN input data 20 and provides DouT output data. The volatile memory 202 also receives for example an equalization signal EQU described in more detail below. Although not shown in FIG. 2, the volatile memory 202 may receive one or more other signals, such as a clock input, test mode signals, and so on. An output Q of the volatile memory 202, which may correspond to the output signal DouT, is for example provided on a line 206 to the non-volatile memory 204. This signal enables the data of the volatile memory 202 to be stored in the memory. nonvolatile memory 204 by programming the resistive state of one or more resistive elements. For this purpose, the non-volatile memory 204 is coupled to the supply voltage rail VDDH, as previously described, in connection with Figs. 1A and 1B. During a restoration phase, a signal - RESTORE on an input of the nonvolatile memory 204 is activated for example, and the nonvolatile data DNv stored by the nonvolatile memory 204 is restored in the volatile memory 202 by Via a line 208, so that they can be accessed via the data output DouT of the volatile memory 202. The volatile memory 202 is for example capable of normal operation during which data can be stored and accessed in a standard volatile manner. In addition, the nonvolatile memory 204 may be used to provide nonvolatile backup of the data stored by the volatile memory 202. For example, in preparation for a sleep mode of the memory device 200, the nonvolatile memory 204 is controlled. in order to store the current data held in the volatile memory 202. At the end of the sleep period, the volatile and non-volatile memories 202, 204 are controlled to restore the data in the volatile memory 202. Figure 3 illustrates schematically the nonvolatile memory 204 of FIG. 2 in more detail according to an exemplary embodiment in which the memory comprises a single resistive element 100, which is for example the element of FIGS. 1A and 1B. As will be described in more detail below, alternative configurations may utilize a pair of resistive elements 100 programmed in a complementary manner. The node 102 of the element 100 is coupled to a programming circuit 302, and the node 104 of the element 100 is coupled to a programming circuit 304. The circuit 302 comprises, for example, a current mirror consisting of a reference branch comprising a P-channel MOS transistor (PMOS) 306, coupled by its main conduction nodes between the VDDH supply rail and an intermediate node 308. The node 308 is for example coupled to the gate of the PMOS transistor 306 and to ground via the main conduction nodes of an N-channel MOS transistor (NMOS) 310, which is controlled at its gate by an establishment signal S, and forms a current source. The current mirror also comprises another branch comprising a PMOS transistor 312, coupled between the supply rail VDDH and the node 102 of the resistive element 100, and having its gate coupled to the gate of the transistor 306. The dimensions of the transistors 306 and 312 of the current mirror are for example identical, which implies that the current in each branch of the current mirror will be substantially the same. Alternatively, transistors 306 and 312 could have different dimensions to each other. For example, transistor 312 may have a transistor width greater than that of transistor 306, which implies that an upper current will flow in transistor 312 relative to transistor 306. Similarly, circuit 304 includes, for example a current mirror consisting of a reference branch comprising a PMOS transistor 316, coupled by its main conduction nodes between the supply rail VDDH and an intermediate node 318. The node 318 is for example coupled to the gate of the transistor PMOS 316 and grounded through the main conduction nodes of an NMOS transistor 320, which is controlled at its gate by a reset signal R, and constitutes a current source. The current mirror also comprises another branch comprising a PMOS transistor 322 coupled between the supply rail VDDH and the node 104 of the resistive element 100, and having its gate 25 coupled to the gate of the transistor 316. Here again, the For example, the dimensions of transistors 316 and 322 of the current mirror are the same, which implies that the current in each branch of the current mirror will be substantially identical. Alternatively, transistors 316 and 322 could have different dimensions. For example, the transistor 322 may have a transistor width greater than that of the transistor 316, which implies that an upper current will flow in the transistor 322 with respect to the transistor 316. The node 102 is for example further coupled to the transistor 322. by means of the main conduction nodes of an NMOS transistor 324 controlled at its gate by the reset signal R. Similarly, for example, the node 104 is coupled to the earth. via the main conduction nodes of an NMOS transistor 326 5 controlled at its gate by the establishment signal S. The node 102 is also for example coupled to ground via the main conduction nodes of an NMOS transistor 328 controlled at its gate by a restoration signal RESTORE, and the node 104 is for example coupled to the line 208 via an NMO transistor S 330 also controlled at its gate by the RESTORE restoration signal. Alternatively, transistor 328 could be controlled by a signal ACTIVE_REST = NOR (FORM, STORE), where the signals FORM and STORE indicate respectively when a forming operation or a storage operation takes place. Thus, the node 102 is grounded by the transistor 328 not only during the restore operation, but also during the active mode. This prevents the node 102 from floating during the active mode. Of course, in some other embodiments transistors 324 and 328 could be implemented by a single transistor controlled at its gate by a signal equal to the logical OR of R and RESTORE signals, or R and R signals. ACTIVE REST. For example, a control block 332 generates the signals S and R on the basis of the signal Q on the line 206 from the volatile memory 202, and the signal curves FORM and STORE respectively indicating the moment when a training operation 30 and a memorization operation take place. In operation, during a storage operation, the signal STORE is for example activated and the resistive element 100 is for example brought to the low resistive state or reset to the high resistive state as a function of the data value Q of the volatile memory 202. If the resistive element 100 is to be placed in the low resistive state, the signal S is for example activated to make the transistors 310 and 326 conductive, and thereby cause the passage of a current in each branch of the current mirror of the circuit 302. The supply voltage rail VDDH supplies the voltage VsToRE which is applied to the node 102 of the resistive element 100. In the other case, if the element resistive 100 must be reset to the high resistive state, the signal R is for example activated to turn on transistors 320 and 324 and thus cause the passage of currents in each branch of the current mirror circuit 304. Here again, the supply voltage rail VDDH supplies the voltage level V STORE, which is applied to the node 104 of the resistive element 100. In the case of a forming operation, the FORM signal is activated. and the signal S is for example activated, while the signal R remains low. The voltage on the supply voltage rail VDDH is also brought to the level VFoRm, so that this voltage level is applied to the node 102 of the resistive element 100.

The circuits 302 and 304 thus provide voltage boosters during storage and / or training operations, allowing relatively low control signals S and R to be converted into relatively high voltage levels present on the rail. VDDH power supply. In addition, the current mirrors of the circuits 302 and 304 make it possible to set and reset the currents to be applied to program the resistive element 100. During the restoration phase, the signals S and R are for example low, and the RESTORE signal is for example activated in order to couple the resistive element 100 between the line 208 and ground. This will cause the application of a reading voltage VREAD across the resistive element 100, and the current flowing in the element 100 will depend on its programmed resistive state. This current is for example used for programming the state of volatile memory 202, as will be described in more detail below. FIG. 4 schematically illustrates the memory device 200 of FIG. 2 in more detail according to an exemplary embodiment in which the volatile memory 202 is a flip-flop comprising a master latch 402 and a slave latch 404. In the example In FIG. 4, the non-volatile memory 204 is coupled to the slave latch 404, but in alternative embodiments it could be coupled to the master latch 402. The master latch 402 includes, for example, a multiplexer. 406 receiving on one of its data inputs the DIN signal, and on the other of its data inputs a test signal TI. A selection is made between these signals 15 by a selection signal TE. The output of the multiplexer 406 is coupled, via an inverter 408, to a flip-flop consisting of a pair of inverters 410, 412, cross-coupled between storage nodes 414, 416. 412 are for example controlled by complementary timing signals C and ON generated on the basis of a clock signal CP supplied to the flip-flop. For example, the CP signal is inverted by an inverter to generate the ON signal, and the ON signal is inverted by another inverter to generate the C signal. The node 416 is coupled to the slave latch 404.

The slave latch 404 includes, for example, an inverter 418 having its input coupled to the node 416 of the master latch 402. The output of the inverter 418 is coupled to another latch 420 consisting of a pair of latches. Inverters 421, 422 cross-coupled between storage nodes 424, 426. Inverters 418 and 422 are for example controlled by the complementary time signals C and ON. The node 426 for example provides the output signal Q of the volatile device 202. The storage node 424 is for example coupled to an inverter 428, which provides the output data of the volatile device 202.

The nonvolatile memory 204 comprises, for example, a pair of non-volatile memory circuits NVM1 and NVM2, each of which for example comprises the circuit of FIG. 3, except that the control block 332 of each circuit is replaced by A common control block 430 in FIG. 4. In addition, the transistors 310 and 326 in the circuit NVM1 are controlled by a signal S1, and the transistors 320 and 324 are controlled by a signal R1. Similarly, the transistors 310 and 326 in the NVM2 circuit are controlled by a signal S2, and the transistors 320 and 324 are controlled by a signal R2. The control block 430 receives the signals Q, STORE and FORM, and generates the signals S1, S2, R1 and R2 to control the circuits NVM1 and NVM2. The NVM1 and NVM2 circuits are coupled to the slave latch 404, and in particular to the latch 420, via lines 208A and 208B respectively. The latch 420 also receives for example the EQU equalization signal, as will be described in more detail below.

Figure 5 schematically illustrates control block 430 for generating signals Si, S2, R1 and R2 in more detail according to an exemplary embodiment. The signal Q is for example coupled to the input of an inverter 502, the output of which is coupled to the input of another inverter 504, and in the form of a signal Qs to an input of an AND gate. The output of the inverter 504 provides a signal Qs, and is coupled to an input of a two-input AND gate 508. The other inputs of the AND gates 506 and 508 receive the signal STORE. The outputs of the AND gates 506 and 508 respectively provide the reset signals R1 and R2, and are respectively coupled to inputs OR gates with two inputs 510 and 512 respectively. The other inputs of the OR gates 510, 512 are coupled to the FORM signal. The outputs of the OR gates 510, 512 respectively provide the establishment signals S1 and S2.

In alternative embodiments, rather than the Qs and Qs signals being generated by the inverters 502 and 504 based on the Q signal, they could be provided directly by the nodes 426 and 424 respectively of the flip-flop 5. FIG. 6 schematically illustrates lock latch 420 in more detail according to an exemplary embodiment. The inverter 421 comprises, for example, PMOS transistors 602, 604 and NMOS transistors 606, 608 coupled in series with each other via their main conduction nodes between the supply voltage rail VDD and the line 208A. The line 208A is for example coupled to ground via an NMOS transistor 609 controlled at its gate by the inverse of the RESTORE signal. The PMOS transistor 602 and the NMOS transistor 608, for example, have their gates coupled to the storage node 424, and the transistors 604 and 606, for example, have their gates coupled to the ground and to VDD respectively, so that they are activated when the circuit is powered. An intermediate node 610 between the transistors 604 and 606 is coupled to the storage node 426. The inverter 422 comprises, for example, PMOS transistors 612, 614 and NMOS transistors 616, 618 coupled in series with each other via their main conduction nodes between the supply voltage VDD rail and the 208B line. The line 208B is for example coupled to ground via an NMOS transistor 619 controlled on its gate by the inverse of the RESTORE signal. The PMOS transistor 612 and the NMOS transistor 618, for example, have their gates coupled to the storage node 426, and the transistors 614 and 616, for example, have their gates coupled to the signals C and ON, respectively. An intermediate node 620 between the transistors 614, 616 is coupled to the storage node 424. Optionally, a voltage equalization circuit 622 is also provided, including a PMOS transistor 624 coupled through its main conduction nodes between The memory nodes 424 and 426, respectively, are stored in the memory nodes 424 and 426 respectively. The circuit 622 also includes, for example, a PMOS transistor 626 coupled via its main conduction nodes between the storage node 424 and the supply voltage rail VDD, and a PMOS transistor 628 coupled via its main conduction nodes between the storage node 426 and the supply voltage rail VDD. The gates of the transistors 624, 626 and 628 are all for example controlled by the equalization signal EQU.

Rather than including two non-volatile memory circuits NVM1 and NVM2, the memory device 200 of FIG. 4 could be adapted to include a single non-volatile memory circuit, for example the circuit of FIG. 3. This single memory circuit is for example coupled to only one of the inverters 421, 422 of the slave latch 404, and the other inverter is for example coupled to a reference resistance level approximately equal to the intermediate level between the resistors of the high and low resistive states. . Thus, during the restore operation, the programmed resistive state of the single resistive element 100 is capable of establishing the voltage state at the lock nodes 424 and 426 of the latch. The operation of the memory device of FIG. 4 will now be described in more detail with reference to the timing diagram of FIG. 7. FIG. 7 illustrates examples of the supply voltage levels (SUPPLY) on the supply rail. VDDH according to a first option (OPTION 1) and according to a second option (OPTION 2) and on the VDD supply rail. In addition, FIG. 7 illustrates an example of the flip-flop CP signal (FF), and FORM, STORE, EQU, and RESTORE non-volatile memory (NVM) signals. We will first describe the case in which the VDDH voltage rail is controlled according to the first option. The voltage VDDH and the signals FORM, STORE and RESTORE are for example all low initially, and the voltage rail VDD and the voltage EQU are for example VDD. The CP signal normally clock, and thus the flip-flop is in an active mode (ACTIVE), in which data enters the flip-flop and is stored in a volatile manner. A training operation (FORMING) is then illustrated in FIG. 7, during which the voltage on the supply rail VDDH is brought to a level VFoRm, and the signal FORM is activated. The signal CP is for example brought to a low level during the fotmation operation. In the example of Figure 7, the training operation is followed by a return to active mode. A storage operation (STORE) is then illustrated in FIG. 7, during which the voltage on the VDDH supply rail is brought to a VSTORE level, and the STORE signal is activated. The data stored in the volatile portion of the flip-flop are thus used to program the resistive elements 100 of each NVM1 and NVM2 circuit in a complementary manner.

A sleep operation (SLEEP) is then illustrated in FIG. 7, during which the supply rails VDDH and VDD are both brought to a low level, and all the other signals also go low. At the end of the sleep operation, a restore operation is performed, during which the VDD voltage is brought back to the high state, and the RESTORE signal is also activated. The signal EQU is also low during the first portion of the restoration phase, so that the voltages on the storage nodes 424, 426 of the latch 420 are equalized to a level close to the supply voltage V DD. When the signal EQU is then brought to the high level, the voltages on the storage nodes will diverge to the nearest stable state based on the programmed resistance of the resistive element 100 in each of the NVM1 and NVM2 circuits.

Figure 7 finally shows a return to the active mode at the end of the restore operation, during which the data restored in the slave latch 404 of the flip-flop will be accessed.

According to the second option (OPTION 2) shown in FIG. 7, the voltage on the supply rail VDDH is for example permanently at the level of VSTORE, except during the training operation and the sleep phase. Since the forming operation is performed only once, this means that the level of the V STORE voltage can be maintained at a constant level most of the time. FIG. 8 schematically illustrates the non-volatile memory 204 of FIG. 2 in more detail according to an alternative embodiment similar to that of FIG. 3, but in which the programming circuits 302 and 304 are used to program a pair of elements In particular, the circuit 302 is for example coupled to the node 102 of the element 100A, denoted 102A in FIG. 8, and the circuit 304 is for example coupled to the node 102 of the element 100B, denoted 102B in FIG. In addition, the nodes 104 of the elements 100A and 100B, respectively referenced 104A and 1043 in FIG. 8, are coupled to each other and to the ground by means of an NMOS transistor 802 controlled on its gate by the signal FORM, and through an NMOS transistor 804 controlled on its gate 25 by the signal RESTORE. The node 102A is for example coupled to the line 208A via the main conduction nodes of a transistor 330A, which is for example an NMOS transistor, and the node 1023 is for example coupled to the line 2083 by 303. intermediate of the main conduction nodes of a transistor 3303, which is also for example an NMOS transistor. Transistors 330A and 330B are for example controlled by the signal RESTORE. The elements 100A and 100B are thus programmed together in a complementary manner, by activating either the current source 310 of the circuit 302 and the transistor 326, or the current source 320 of the circuit 304 and the transistor 324. the circuits 302 and 304, the transistor 310 is controlled by a control command signal C1, and the transistor 326 is controlled by a control signal C3. The control signals C1 and C3 are for example activated when the element 100A must be put in the low resistive state and the element 1003 must be brought back to the high resistive state. The signal C1 is also for example activated during a forming operation of the elements 100A, 100B, but not the control signal C3. Similarly, the transistor 324 is controlled by a control signal C2 and the transistor 320 is controlled by a control signal C4. The control signals C2 and C4 are for example activated when the element 100B is to be put in the low resistive state and the element 100A must be brought back to the high resistive state. The signal C4 is also for example activated during a formation operation of the elements 100A, 1003, but not the signal C2. The operation of the circuit of FIG. 8 is similar to that of the nonvolatile memory 204 of FIG. 4, except that the voltage level V STORE is, for example, at an unsymmetrical level, for example between 2 and 6 V when seen. since two resistive elements 100A, 100B are programmed at the same time. During the forming operation, the transistor 802 is for example activated so that the forming voltage VFoRm 25 on the supply rail VDDH is applied to the nodes 102A, 102B of each resistive element 100A, 100B, respectively. FIG. 9 diagrammatically illustrates the nonvolatile memory 204 of FIG. 2 in more detail according to an alternative embodiment similar to that of FIG. 3, but in which a cascade of transistors is used to reduce the voltages applied across the terminals of certain transistors. . In particular, the programming circuit 302 comprises, for example, a PMOS transistor 902 and a NMOS transistor 904 coupled in series through their main conduction nodes 35 between the node 308 and the transistor 310. Similarly, a 3035998 B13587 The PMOS transistor 906 is, for example, coupled by its main conduction nodes between the transistor 312 of the current mirror and the node 102 of the resistive element 100. An NMOS transistor 908 is also for example coupled via its 5 main conduction nodes between the node 102 and the transistor 324. The transistors 902, 904, 906 and 908 are for example controlled at their gates by a voltage level of VDDH / 2, or by another level of intermediate voltage greater than the ground voltage and less than the voltage on the supply voltage VDDH rail. In the programming circuit 304, a PMOS transistor 912 and an NMOS transistor 914 are, for example, coupled in series through their main conduction nodes between the node 318 and the transistor 320. Similarly, a PMOS transistor 916 is for example coupled by its main conduction nodes between the transistor 322 of the current mirror and the node 104 of the resistive element 100. An NMOS transistor 918 is also for example coupled via its main conduction nodes between the Node 104 and transistor 326. Transistors 912, 914, 916 and 918 are for example controlled at their gates by a voltage level of VDDH / 2, or by another level of intermediate voltage higher than the ground voltage. and lower than the voltage on the supply voltage rail VDDH.

In addition, an NMOS transistor 920 is for example coupled via its main conduction nodes between the node 102 and the transistor 328, and an NMOS transistor 922 is for example coupled via its main conduction nodes. between the node 104 and the line 208. The transistors 920 and 922 are for example controlled by the supply voltage VDD. It will be apparent to those skilled in the art that the embodiment of Fig. 8 could be modified to include some or all of the cascaded transistors of Fig. 9.

An advantage of the embodiments described herein is that a relatively high voltage level can be applied to a readily programmable resistive element even if the circuit transistors have a lower voltage limit at that level. Of voltage. With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. For example, it will be apparent to those skilled in the art that the VDD, V STORE and VFoRm supply voltages in the various embodiments could be at any level, for example between 1 and 6 V, and rather than being at 0 V, the ground voltage could also be considered as a supply voltage which could be at any level, such as a negative level. In addition, it will be apparent to those skilled in the art that in each of the embodiments described herein, some or all of the NMOS transistors could be replaced by PMOS transistors and / or some or all of the PMOS transistors. could be replaced by NMOS transistors. The way in which the circuits could be implemented using only PMOS transistors or only NMOS transistors will be clear to those skilled in the art, for example by reversing the supply rails. In addition, although transistors based on MOS technology have been described herein, in alternative embodiments other transistor technologies, such as bipolar technology, could be used. In addition, it will be apparent to those skilled in the art that the various elements described in connection with the various embodiments could be combined, in alternative embodiments, in any combination.

Claims (12)

REVENDICATIONS1. A nonvolatile memory comprising: a first resistive element (100, 100A) having a first and a second node (102, 104); a programming circuit (302, 304) for programming the first resistive element (100) to take one of a first and a second resistive state (LRS, HRS), the programming circuit comprising: - a first current mirror (306, 312) coupled to a first supply voltage rail (VDDH) and having a first branch (312) coupled to the first node (102) of the resistive element (100, 100A), and a second branch (306) coupled to a first current source (310); and - a first transistor (326) coupling the second node (104) of the first resistive element to a second power supply (GND) rail. The non-volatile memory according to claim 1, wherein the programming circuit (302, 304) further comprises: - a second current mirror (316, 322) coupled to the first power supply voltage (VDDH) rail and having a third branch (322) coupled to the second node (104) of the first resistive element (100, 100A) or the first node of a second resistive element (100B), and a second branch (316) coupled to a second source of current (320); and a second transistor (324) coupling the first node (102) of the first resistive element (100, 100A) to the second supply voltage rail (GND). A non-volatile memory according to claim 2, further comprising a control circuit (332) adapted to activate, on the basis of a data bit to be stored by the first resistive element (100, 100A), the first source current (310) and the first transistor (326) or the second current source (320) and the second transistor (324). 3035998 313587 - DD15341ST 23 The non-volatile memory according to claim 3, further comprising a third transistor (330) coupled between the first or second node of the first resistive element (100, 100A) and an output line (208, 208A) of the non-volatile memory. volatile. A non-volatile memory according to any one of claims 1 to 4, further comprising a second resistive element (100B) having a first and a second node (102B, 104B), the second node (1043) of the second resistive element ( 100B) being coupled to the second node (104A) of the first resistive element. The non-volatile memory according to claim 5, further comprising a fourth transistor (802) coupled between the second node of the first and second resistive elements and the second supply voltage (GND) rail, and a control circuit (332). ) adapted to activate the fourth transistor during a forming operation of the first and second resistive elements (100A, 1003). A non-volatile memory according to any one of claims 1 to 6, wherein the first branch of the first current mirror (302) is coupled to the first node of the resistive element (100, 100A) via a fifth transistor (906) controlled at its control node by an intermediate voltage level (VDDH / 2) between the voltages of the first and second supply voltage rails. A memory device comprising: a first nonvolatile memory circuit (NVM1) comprising the nonvolatile memory of any one of claims 1 to 7; and a volatile memory (202) comprising a first latch (420) including first and second inverters (421, 422) cross-coupled between first and second storage nodes (424, 426), first or second second node of the first resistive element (100, 100A) of the first nonvolatile memory circuit being coupled to a supply voltage node of the first inverter. The memory device according to claim 8, further comprising a second non-volatile memory circuit (NVM2) comprising the non-volatile memory of any one of claims 1 to 7, the first or second node of the first resistive element ( 100, 100A) of the second non-volatile memory circuit (NVM2) being coupled to a supply voltage node of the second inverter. 10 Memory device according to claim 8 in its dependence on claim 5 or 6, wherein the first or the second node of the second resistive element (100, 100A) of the first non-volatile memory circuit (NVM1) is coupled to a node supply voltage of the second inverter. 15 The memory device according to any one of claims 8 to 10, wherein the volatile memory (202) is a flip-flop, the first latch is a master latch or slave latch flip-flop of the flip-flop. 20 A nonvolatile data storage method comprising: applying by a programming circuit (302, 304) a voltage (V STORE, VFORM) to a first node of a first resistive element (100, 100A), the programming circuit (302, 304) comprising a current mirror having a first branch coupled to the first node (102) and a second branch coupled to a first current source (310), and the voltage being applied by activating the first power source ( 310); and coupling, by a first transistor (326), a second node (104) of the first resistive element to a second supply voltage rail (GND).