EP2987168B1 - Memory cell with non-volatile data storage - Google Patents
Memory cell with non-volatile data storage Download PDFInfo
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- EP2987168B1 EP2987168B1 EP14722276.4A EP14722276A EP2987168B1 EP 2987168 B1 EP2987168 B1 EP 2987168B1 EP 14722276 A EP14722276 A EP 14722276A EP 2987168 B1 EP2987168 B1 EP 2987168B1
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- 230000015654 memory Effects 0.000 title claims description 119
- 238000013500 data storage Methods 0.000 title description 2
- 230000006870 function Effects 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 8
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 13
- 230000000630 rising effect Effects 0.000 description 11
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 8
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 5
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 5
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 5
- 230000004913 activation Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000005291 magnetic effect Effects 0.000 description 5
- 102100035420 DnaJ homolog subfamily C member 1 Human genes 0.000 description 4
- 101000804122 Homo sapiens DnaJ homolog subfamily C member 1 Proteins 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 229930091051 Arenine Natural products 0.000 description 1
- 229910003321 CoFe Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229940082150 encore Drugs 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0072—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a ferroelectric element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
Definitions
- the present disclosure relates to a memory cell and a method for nonvolatile storage of a data value in a memory cell.
- the present description relates to a memory cell and a method comprising one or more resistive elements that can be programmed by the direction of a current.
- resistive elements are programmable to take one of a plurality of different resistive states.
- the programmed resistive state is maintained even when a supply voltage of the memory cell is disconnected, and therefore data may be stored by such elements in a non-volatile manner.
- resistive elements have been proposed, some of which may be programmed by the direction of a current passed through the resistive elements.
- An example of such a resistive element programmable by a current is an STT (spin transfer torque) element, which is based on magnetic tunnel junctions (MTJ).
- STT spin transfer torque
- the memory cells based on programmable resistive elements tend to be less compact than other types of memory cells such as those of random access memory (RAM).
- RAM random access memory
- An object of embodiments of the present description is to at least partially meet one or more needs of the prior art.
- a memory cell comprising: first and second resistive elements, at least one of them being programmable to take one of at least two resistive states, a data value being represented by the resistors relative first and second resistive elements, the first resistive element being coupled between a first storage node and a first intermediate node, the second resistive element being coupled between a second storage node and a second intermediate node; a first transistor coupled between the first storage node and a first supply voltage; a second transistor coupled between the second storage node and the first supply voltage, a control node of the first transistor coupled to the second storage node and a control node of the second transistor coupled to the first storage node; a third transistor coupled between the first and second intermediate nodes; a fourth transistor coupled by its main current nodes between the first storage node and a data input node; and a control circuit arranged, during a writing phase, to activate the third and fourth transistors and to couple the data input node to a second supply voltage through a first circuit block
- the first circuit block comprises at least one transistor coupled between the data input node and the second supply voltage and controlled by input data of the memory cell.
- the memory cell further comprises a second circuit block comprising at least one transistor coupled between the data input node and the first supply voltage and controlled by the input data of the memory cell. .
- the first and second circuit blocks are arranged to apply to the input data at least one of the logical functions of the group comprising: a multiplexing function; a NOT function; a NON OR function; a NAND function; a NOT OR EXCLUSIVE function; an OR function an AND function; and an EXCLUSIVE OR function.
- the memory cell further comprises a fifth transistor coupled between the second storage node and the second supply voltage, the control circuit being furthermore arranged, during another write phase, to activate the third and fifth transistors for generating a programming current in a second direction in the first and second resistive elements for programming the resistive state of at least one of the elements.
- the memory cell further comprises a sixth transistor coupled between the second storage node and another data input node, the control circuit being further arranged, for another write phase, to activate the third and sixth transistors and to couple the other data input node to the second power supply voltage via another circuit block to generate a programming current in a second direction in the first and second resistive elements for programming the resistive state of at least one of the elements.
- the memory cell further comprises an inverter coupled between the first storage node and the second storage node, the control circuit being furthermore arranged, during another write phase, to activate the third and fourth transistors and for coupling the data input node to the first power supply voltage via the second circuit block to generate a programming current in a second direction in the first and second resistive elements for programming the state resistive of at least one of the elements.
- each of the first and second transistors is connected to the first supply voltage.
- At least one of the first and second resistive elements is one of the following: a spin transfer torque element having anisotropy in the plane; a spin transfer torque element having anisotropy perpendicular to the plane; a redox element (RedOx); a ferroelectric element; and a phase change element.
- each of the first and second transistors comprises a substrate node
- the control circuit is further arranged to couple the substrate node of at least one of the first and second transistors to a third voltage. supply different from the first supply voltage while the data input node is coupled to the second supply voltage.
- the memory cell further comprises a seventh transistor coupled between the first intermediate node and the second supply voltage; and an eighth transistor coupled between the second intermediate node and the second supply voltage, the seventh and eighth transistors being for example adapted to have a threshold voltage lower than that of the first and second transistors.
- a memory device comprising: an array of the aforementioned memory cells, the data input nodes of the memory cells being coupled to first bit lines of the memory device.
- a synchronous memory device comprising the aforementioned memory cell and another memory cell coupled in series with the memory cell, the other memory cell comprising two inverters cross-coupled.
- a method for non-volatile storage of a data value in a memory cell comprising first and second resistive elements, at least one of which is programmable to take one of at least two resistive states, a data value being represented by the relative resistances of the first and second resistive elements, the first resistive element being coupled between a first storage node and a first intermediate node, the second resistive element being coupled between a second resistive element storage node and a second intermediate node; a first transistor coupled between the first storage node and a first supply voltage; a second transistor coupled between the second storage node and the first supply voltage, a control node of the first transistor coupled to the second storage node and a control node of the second transistor coupled to the first storage node; a third transistor coupled between the first and second intermediate nodes; a fourth transistor coupled by its main current nodes between the first storage node and a data input node, the method comprising: enabling the third and fourth transistors; coupling the data input
- connection is used to designate a direct connection between one element and another, while the term “coupled” implies that the connection between the two elements can be made directly, or via an intermediate element, like a transistor, a resistor or some other component.
- the figure 1 reproduces the figure 7 of the publication entitled " Spin-MTJ Based Non-Volatile Flip-Flop ", Weisheng Zhao et al., Proceedings of the 7th IEEE International Conference on Nanotechnology August 2-5, 2007, Hong Kong .
- the latch 100 represented in figure 1 includes a master register and a slave register.
- the master register includes MTJ1 and MTJO magnetic tunnel junction devices, programmable by a current.
- the MTJ1 device is connected between an intermediate node 104 and an interconnection node 102.
- the MTJ0 device is connected between an intermediate node 106 and the interconnection node 102.
- the interconnection node 102 connects MTJ devices MTJ0 and MTJ1.
- the intermediate node 104 is further coupled to a supply voltage Vdd via two series-connected transistors MN1 and MP1 forming a first inverter.
- the intermediate node 106 is also coupled to the supply voltage Vdd via two transistors MP0 and MN0 coupled in series and forming a second inverter.
- the first and second inverters are cross-coupled to each other, and the output of the second inverter is connected to the slave register.
- a transistor MN2 is coupled between the gate nodes of the transistor
- An MN5 transistor is coupled between the intermediate node 104 and the supply voltage Vdd
- a transistor MN6 is coupled between the intermediate node 104 and the ground.
- a transistor MN3 is coupled between the intermediate node 106 and the supply voltage Vdd
- a transistor MN4 is coupled between the intermediate node 106 and the ground.
- An MN7 transistor is coupled between the intermediate node 102 and the ground. The transistors MN3 to MN6 allow the passage of a current in the resistive elements MTJ1 and MTJ0 in one direction or the other in order to program the resistive states of the MTJ devices. During this programming phase, the transistor MN7 is used to disconnect the node 102 from the ground.
- a pair of NOR gates and an inverter on the left side of the figure 1 which are controlled by an input signal, a clock signal Clk and an activation signal EN, generate signals for controlling the transistors MN3 to MN6.
- a disadvantage of the circuit of the figure 1 is that the master register comprises a total of 10 transistors, ignoring those of the NOR gates and the inverter.
- FIG 2 illustrates a memory cell 200 according to an exemplary embodiment of the present description not falling under the protection of the appended claims.
- the memory cell 200 includes resistive elements 202 and 204, each of which can be programmed to take one of a plurality of resistive states.
- the resistive elements 202 and 204 may be of any type of resistance switching element for which resistance is programmable by the direction of a current being passed therethrough.
- the resistance switching elements 202, 204 are spin transfer torque elements having anisotropy in the plane or perpendicular to the plane, as described in more detail in the publication entitled " Magnonic spin-transfer torque MRAM with low power, high speed, and error-free switching, N. Mojumder et al., IEDM Tech Digest (2010) ), and in the publication " Electric toggling of magnets ", E.
- the resistive elements could be those used in RedOx-type RAM (RAM redox) type RAM memories, which are for example described in more detail in the publication entitled “ Redox-Based Resistive Switching Memories - Nanoionic Mechanisms, Prospects and Challenges, "Rainer Waser et al., Advanced Materials 2009, 21, pp. 2632-2663. .
- the resistive elements could be those used in memories of FeRAM type (ferroelectric RAM) or PCRAM (phase-change RAM).
- a data bit is for example stored in the memory cell nonvolatile way by putting one of the elements to a relatively high resistance (R max ), and the other to a resistance relatively low (R min ).
- the element 202 is programmed to have a resistor R max and the element 204 a resistor R min representing a value of the data bit, and as represented by the references R min and R max in parentheses, opposite programming of the resistance values stores the opposite value of the data bit.
- Each of the resistance switching elements 202, 204 has for example only two resistive states corresponding to the high and low resistors R max and R min , but the exact values of R min and R max may vary depending on conditions such as the process, materials, temperature variations, etc.
- the non-volatile data bit represented by the resistive elements 202, 204 depends on which of the resistive elements has the resistance R max or R min , in other words, depends on the relative resistances.
- the resistive elements 202, 204 are for example selected so that R max is always significantly greater than R min , for example greater than at least 20 percent.
- the ratio between the resistance R max and the resistance R min is for example between 1.2 and 10000.
- R min is for example in the region of 2 kilo-ohms or less, and R max is for example in the region of 6 kilo-ohms or more, although other values are possible.
- the other resistive element has for example a fixed resistance at an intermediate level about halfway between R min and R max , for example equal to a tolerance of 10 percent, at (R min + (R max -R min ) / 2).
- one of the resistive elements 202, 204 could correspond to a fixed value resistor.
- one of the resistive elements 202, 204 could consist of two programmable resistive elements coupled in parallel and having opposite orientations, so whatever the direction in which each element is programmed, the resistance value remains relatively constant at the intermediate level.
- the resistive element 202 is coupled between a storage node 206 and an intermediate node 208.
- the resistive element 204 is coupled between a storage node 210 and a storage node 210. intermediate node 212.
- the storage nodes 206 and 210 store Q voltages and Q respectively.
- Two inverters are cross-coupled between the storage nodes 206 and 210 to form a register.
- Each inverter consists of a single transistor 214, 216 respectively.
- the transistor 214 is for example an N-channel MOS transistor (NMOS) coupled by its main current nodes between the node 206 and another node 218.
- the transistor 216 is for example an NMOS transistor coupled by its main current nodes between the storage node 210 and the other node 218.
- a control node of the transistor 214 is coupled to the storage node 210, and a control node of the transistor 216 is coupled to the storage node 206.
- the node 218 is either connected to the mass, or coupled to ground via the main current nodes of an NMOS transistor 219, represented by dashed lines in figure 2 .
- the intermediate nodes 208 and 212 are coupled to each other via the main current nodes of an NMOS transistor 220.
- the transistor 220 receives on its control node a signal AZ described in more detail below.
- the node 208 is further coupled to a supply voltage V DD via the main current nodes of a P-channel MOS transistor 222.
- the node 212 is coupled to the voltage of the second voltage.
- supply V DD via the main current nodes of a PMOS transistor 224.
- the control nodes of the PMOS transistors 222 and 224 are coupled together to a transfer signal TR described in more detail below.
- the storage node 206 is further coupled to the supply voltage V DD via the main current nodes of a PMOS transistor 226, and to the ground via the main current nodes of a transistor. NMOS 228. Transistors 226 and 228 receive on their control nodes write signals WP1 and WN1 respectively.
- the storage node 210 is coupled to the supply voltage V DD through the main current nodes of a PMOS transistor 230, and to ground through the main current nodes of an NMOS transistor 232. The transistors 230 and 232 receive on their control nodes of write signals WP2 and WN2 respectively.
- the figure 2 also illustrates a control block 234, supplying the control signals TR, AZ, WP1, MN1, WP2 and WN2 to the corresponding transistors of the memory cell 200.
- these control signals are for example generated on the nonvolatile D NV database received on an input line 236, a WPH write phase signal received on an input line 238, and a TPH transfer phase signal received on a line d entry 240.
- the transistors MP1 and MP0 are coupled to the supply rail Vdd and have the role of maintaining a high state on one of the nodes of the register formed by the four transistors MN0, MN1, MP0 and MP1.
- cell 200 of the figure 2 in which each inverter is implemented by a single transistor 214, 216, the high state of Q or Q is maintained by a leakage current flowing in the PMOS transistors 222 or 224, and / or in the PMOS transistors 226 and 230.
- the threshold voltages of the PMOS transistors 222, 224 and / or 226, 230 are chosen to be smaller than those of the NMOS transistors 214, 216, 228, 232 so that when they are in the non-conductive state, the leakage current in the transistors 222, 224 and / or 226, 230 is greater than that in the transistors 214, 216, 228, 232, thus keeping the corresponding node 206 or 210 at a voltage high enough to be seen as a logic state above.
- the leakage current I offP flowing in the PMOS transistor 222, 224 and / or 226, 230 when a high level voltage is applied to the corresponding gate nodes is greater than the offN I leakage current flowing in. the NMOS transistor corresponding 214, 216, 228 or 232 when a low level voltage is applied to its gate node.
- the threshold voltages of the PMOS transistors 222, 224, and / or 226, 230 are chosen to be in the range of 0.3 to 0.5 V, whereas the threshold voltages of the transistors NMOS 214, 216, 228, 232 are the range of 0.4 to 0.6 V.
- the ratio I 0ffp / I Offn is selected for example to be greater than 25, and preferably greater than 100.
- the memory cell 200 is able to store, in a volatile manner, a data bit which is independent of the programmed resistive states of the elements 202 and 204.
- the register formed by the transistors 214 and 216 will keep any memorized state.
- Figures 3A and 3B are timing diagrams representing signals in the memory cell of the figure 2 during a transfer phase.
- Figures 3A and 3B illustrate the Q data signals and Q present on the storage nodes 206 and 210, the transfer phase signal TPH, the transfer signal TR, and the signal AZ during a transfer phase of the circuit.
- the transfer phase corresponds to an operation consisting in transferring the data represented by the programmed resistive states of the resistive elements 202 and 204 to the storage nodes 206, 210.
- the data is transformed by a representation by the programmed resistive state. in a representation by voltage levels on the storage nodes 206 and 210.
- the transfer phase involves establishing the levels of the Q voltages and Q on memory nodes 206 and 210 based on the programmed resistive states.
- the resistive element 202 has been programmed to have a high resistance R max , and the resistive element 204 a low resistance R min .
- the control signals WP1, WP2 are high and the control signals WN1, WN2 are low such that the corresponding transistors 226 to 232 are all non-conductive.
- the figure 3A corresponds to a case in which the voltages Q and Q are initially in a high state and in a low state respectively.
- the term "high state” is used herein to designate a voltage level close to or equal to the level of the supply voltage V DD
- the term “low state” is used herein to designate a voltage level close to or equal to the mass voltage.
- the transfer signal TR is for example initially high, so that the transistors 222 and 224 are non-conductive.
- the signal AZ is for example initially low, so that the transistor 220 is non-conductive.
- the transfer phase signal TPH which is for example initially low, is activated as represented by a rising edge 302, triggering shortly after a falling edge of the transfer signal TR, and a rising edge of the signal AZ, by example shortly after the falling edge of the transfer signal TR.
- the transistors 220, 222 and 224 of the figure 2 are all activated, inducing a current in the left branch of the memory cell 200 which passes into the transistor 222, in the resistive element 202 and the transistor 214, and a current in the right branch of the memory cell which passes through the transistor 224 in the resistive element 204 and the transistor 216.
- the current in the branch on the left is lower than the current in the branch of right.
- these currents for example cause the voltage to descend on the storage node 206 and its establishment at a level V 1 less than a metastability level M, and the rise of the voltage on the storage node 210 to a maximum V-level 2 above the metastability level M.
- the metastability level M is a theoretical voltage level located approximately mid-way between the high and low voltage states, representing the level from which there would be an equal probability that Q switches to high or low state.
- Activation of the signal AZ to turn on the transistor 220 has the effect of accelerating the descent of the voltage level Q, and the rise of the voltage level Q .
- the signal AZ is then brought to the low state, and the transfer signal TR is brought back to the high state on a rising edge 304, so that the levels Q and Q go to their nearest stable state, which in the example of the figure 3A corresponds to the low Q state, Q above.
- the levels V 1 and V 2 and the final stable state, will depend on factors such as the resistance to the conductive state of the transistors 214, 216, 222 and 224.
- the transfer phase signal TPH goes low to complete the transfer phase.
- the figure 3B corresponds to a case in which Q voltages and Q are initially in a low state and a high state respectively.
- the transfer phase signal TPH, the transfer signal TR and the signal AZ have the same shapes as those of the figure 3A and will not be described again.
- the difference from the figure 3A is that when the signal TR is brought to the low state and the signal AZ is brought to the high state, the voltage Q goes up to the level V 1 , and the voltage Q goes down to level V 2 .
- the Q levels and Q go to their nearest stable state, which in the example of the figure 3B corresponds to the low Q state and Q above.
- the levels V 1 and V 2 and the final stable state, will depend on factors such as the resistors in the conductive state of transistors 214, 216, 222 and 224.
- the Figures 4A and 4B are timing diagrams illustrating examples of the signals D NV , WPH, AZ, WP1, WN1, WP2 and WN2 in the circuit of the figure 2 during a writing phase of the resistive states of the resistive elements 202 and 204. Although this is not represented in the Figures 4A and 4B during the write phase, the transfer signal TR for example remains high so that the transistors 222 and 224 are non-conductive.
- the write phase involves the passage of a current in each of the resistive elements 202, 204 through the transistor 220, either in the direction from the storage node 206 to the storage node 210, or in the opposite direction .
- the resistive elements 202 and 204 are oriented so that, for a given direction of the current, they will be programmed to have opposite resistances.
- each resistive element 202, 204 can be oriented in one of two ways between the storage node 206, 210 corresponding and the intermediate node 208, 212 corresponding. In the case of an STT element, the orientation is determined by the order of a fixed layer and a storage layer, as will be described in more detail below.
- the elements 202, 204 are both for example oriented in the same way between these corresponding nodes, for example each having its fixed layer located closest to the storage node 206, 210 corresponding, so that they have opposite orientations by relative to a write current passing from the storage node 206 to the storage node 210 or vice versa.
- the signals AZ, WN1 and WN2 are low, and the signals WP1 and WP2 are high, so that the transistors 220 and 226 to 232 are all non-conductive.
- the data signal D NV on the input line 236 of the control circuit 234 is for example first set to the value which must be programmed in the memory cell.
- the value is the logic state "1" and the data signal D NV for example starts low, and goes to a high value on a rising edge 402.
- the WPH write phase signal on the input line 238 of the control circuit 234 then goes high on a rising edge 404, initiating the start of the write phase. This triggers, shortly after, a rising edge of the signal AZ, so that the transistor 220 is activated, coupling between them the nodes 208 and 212.
- the signals WP1, WN1, WP2 and WN2 are set to appropriate values to cause a current to flow through the resistive elements 202 and 204 in a direction that will program their resistances in accordance with the logic "1" data value to be programmed.
- a high state of a data value D NV corresponds to a high value of the voltage Q, in other words to a resistance R min of the element 202, and a resistance R max of the element 204.
- this current direction is generated by causing the signal WP1 to low to activate the transistor 226, and causing the signal WN2 to high to activate the transistor 232.
- the WP1 signal is brought back to the state high, and the signal WN2 is brought to the low state, stopping the write current.
- the signals AZ and WPH are then for example brought to the low state, which ends the writing phase.
- the Figure 4B illustrates an alternative case of a write phase in which the data value to be programmed is a logic state "0", and thus the data signal D NV has a front 406.
- a rising edge 408 of the write signal thus triggers a rising edge of the signal WN1 and a falling edge of the signal WP2, in order to generate a current from the storage node 210, through the resistive elements 204 and 202. to the storage node 206, for a time t W.
- Transistors 220 and 226 to 232 are, for example, sized such that the write current generated by the activation of transistors 226, 220 and 232, or by the activation of transistors 230, 220 and 228, is sufficiently high for programming the resistive states of the elements 202 and 204. Depending on the type and dimensions of the resistive elements 202, 204, such a minimum programming current would for example be of the order of 20 ⁇ A to 1.5 mA.
- the transistors 214, 216 and 222, 224 are for example dimensioned such that during a transfer phase when the transfer signal TR is activated, the level of the current flowing in the resistive elements 202 and 204 is less than that necessary to program their resistive states, for example a level 10 to 90 percent lower than the corresponding write current.
- the transistor MN7 is necessary to disconnect the node 102 from the ground, and thus prevent the write current from flowing to ground.
- the transistor 219 between the node 218 and the ground in the memory cell 200 can be removed. Indeed, since the transistors 214 and 216 forming a register are located between the storage nodes 206, 210 and the ground, the write current will still flow through the resistive elements even if the node 218 is coupled to the mass during the writing phase.
- the figure 5 illustrates a memory cell 500 according to an embodiment variant with respect to that of the figure 2 .
- elements of the memory cell 500 are identical to those of the memory cell 200, and these elements have the same numerical references and will not be described again in detail.
- a difference in memory cell 500 is that transistors 226, 228 and 232 have been removed, leaving only a single transistor 230 dedicated to generating the write current.
- An additional NMOS transistor 502 is coupled by its main current nodes between the storage node 206 and an input circuit 504.
- the transistor 502 is coupled to a data input node 506 of the memory cell.
- the node 506 is coupled to the supply voltage V DD via a circuit block 508 of the input circuit 504, and to the ground via a circuit block 510 of the circuit. 504.
- the transistor 502 is for example controlled by a clock signal CLK.
- the circuit blocks 508 and 510 are controlled by input data D at an input 512.
- the input data D may comprise a single data signal or several data signals for controlling the circuit blocks 508, 510.
- substrate voltage nodes of transistors 214 and 216 are illustrated in FIG. figure 5 .
- the control circuit 234 is also replaced in the memory cell 500 by a control circuit 534, which no longer provides the control signals WN1, WP1 and WN2, and optionally provides substrate voltage levels V BULK1 and V BULK2 , which are applied to the substrate voltage node of transistors 214 and 216 respectively, as will be described in more detail hereinafter.
- a transfer phase can be implemented in the circuit 500 in the same way as has been previously described in connection with the Figures 3A and 3B , and will not be described again in detail.
- the transistor 502 is for example disabled by a low state of the clock signal CLK, so that the storage node 206 is isolated from the input circuit 504.
- a write phase of the resistive elements 202 and 204 is implemented using the PMOS transistor 230 or the input circuit 504, depending on the direction of the write current to be applied.
- the input circuit 504 corresponds to a typical CMOS type device comprising, in the circuit block 508, one or more PMOS transistors coupled to the supply voltage V DD , and in the circuit block 510, one or more NMOS transistors, coupled to ground.
- the input circuit 504 corresponds to an inverter, a multiplexer, a NOR gate, a NAND gate, or other logic circuit.
- the transistor 502 In order to program the resistive elements 202, 204 with a write current flowing from the storage node 206 to the storage node 210, the transistor 502 is activated, and the circuit block 508 is also activated by an appropriate value of data signal D for coupling the intermediate node 506 to the supply voltage V DD .
- the path between the storage node 210 and the ground is for example provided by the transistor 216.
- the transistor 230 is activated.
- the path between the storage node 206 and the ground is either provided solely by the transistor 214, or by the transistor 214 and in addition by the activation of the transistor 502 and the circuit block 510 by an appropriate input data D on entry 512.
- the input circuit 504 in addition to providing a voltage state to the data input node 506 of the memory cell during a write phase, is also used for example as an input or output interface of the memory cell 500.
- the input circuit 504 applies a signal to the data input node 506 to program the data inputs.
- the input data D establishes, for example, the data value to be programmed at the storage nodes 206, 210 in a volatile manner.
- this same data value is for example used to program the resistive states of the elements 202, 204 to store the data value in a non-volatile manner.
- the input circuit 504 may be arranged to read the voltage state Q on the storage node 206, and the input circuit 504 for example also functions as the output circuit of the cell 500 memory.
- the remainder of the memory cell 500 of the figure 5 can only include six transistors.
- the memory cell 500 of the figure 5 could further include transistors 228, 232 and / or 219 of the embodiment of the figure 2 .
- the Figures 6A and 6B illustrate examples of timing diagrams of the signals D NV , WPH, AZ, CLK, WP2, B BULK1 and V BULK2 in the circuit of the figure 5 during a write phase of the resistive states of the resistive elements 202 and 204.
- the signals D NV , WPH, AZ and WP2 are the same as those of the Figures 4A and 4B , and will not be described again in detail.
- the write current is generated by activating only transistors 502 and 220, and applying an appropriate input data D to couple the node 506 at the supply voltage V DD .
- the write current thus flows from the storage node 206, through the resistive elements 202 and 204, to the storage node 210.
- the node 206 being at a relatively high voltage, the transistor 216 is conductive, and so the Write current passes to ground through transistor 216.
- the write current is generated by activating the transistors 220 and 230, and optionally the transistor 502 assuming that the node 506 is coupled to ground via the circuit block 510.
- the write current thus flows to from the storage node 210, through the resistive elements 204 and 202, to the storage node 206.
- the node 210 being at a relatively high voltage, the transistor 214 is conductive, and thus the write current passes to the ground via transistor 214, and optionally also via circuit block 510.
- Controlling substrate voltages V BULK1 and V BULK2 of transistors 214 and 216 can be used to increase the write current, as will now be described.
- the substrate voltages V BULK1 and V BULK2 applied to the transistors 214 and 216 respectively are, for example, grounded , except during the write phase.
- the substrate voltage of one of the transistors is switched to a higher voltage level than ground, for example to the supply voltage V DD , at least during the writing period t W .
- the write current flows from the storage node 206 to the storage node 210. Therefore, the substrate voltage V BULK1 of the transistor 214 is increased to reduce the leakage current passing to ground through the transistor 214.
- the substrate voltage V BULK2 of transistor 216 remains, however, low, so that the transistor 216 remains completely conductive.
- the write current passes from the storage node 210 to the storage node 206. Therefore, the substrate voltage V BULK2 of the transistor 216 is increased to reduce the leakage current passing to ground through the transistor 216 However, the substrate voltage V BULK1 of transistor 214 remains low, so that transistor 214 remains completely conductive.
- FIGS. 7A and 7B illustrate the input circuit 504 of the figure 5 in more detail according to exemplary embodiments.
- the Figure 7A illustrates the case where the input circuit 504 is an inverter, comprising a PMOS transistor 702 coupled by its main current terminals between the node 506 and the supply voltage V DD , and an NMOS transistor 704 coupled by its current terminals. between the node 506 and the mass.
- a low state of the data signal D will cause the coupling of the node 506 to the supply voltage V DD through the transistor 702.
- the Figure 7B illustrates the case where the input circuit 504 is a NAND gate, comprising PMOS transistors 710 and 712 coupled in parallel between the node 506 and the supply voltage V DD , and NMOS transistors 714, 716 coupled in series between the node 506 and the mass.
- the input data D comprises two data signals a and b.
- the transistors 710 and 714 are controlled by the data signal a
- the transistors 712 and 716 are controlled by the data signal b.
- the node 506 is coupled to the supply voltage V DD via the transistor 710 and / or 712.
- circuit blocks 508 and 510 of the input circuit 504 are for example arranged to apply to the input data D at least one of the logical functions of the group comprising: a multiplexing function; a NOT function; a NON OR function; a NAND function; a NOT OR EXCLUSIVE function; an OR function an AND function; and an EXCLUSIVE OR function.
- the figure 8 illustrates a memory cell 800 according to an embodiment variant with respect to the figure 5 .
- Many elements are the same as those of the figure 5 and these elements will not be described in detail.
- the difference in the circuit of the figure 8 is that the NMOS transistors are replaced by PMOS, and vice versa.
- the NMOS transistors 214 and 216 have been replaced by PMOS transistors 814 and 816.
- the node 218 is connected to the supply voltage V DD .
- PMOS transistors 222 and 224 have been replaced by grounded NMOS transistors 822 and 824.
- the PMOS transistor 230 has been replaced by an NMOS transistor 830 coupled to ground.
- the operation of the memory cell of the figure 8 is substantially similar to that of the memory cell of the figure 5 , the only difference being the normal voltage inversions resulting from the NMOS / PMOS exchange.
- a control circuit based on the control circuit 534 of the figure 5 is not illustrated in figure 8 .
- the substrate voltages of one of the transistors 814, 816 which are for example normally at the supply voltage V DD , could be brought to a lower value, for example to ground, during a write phase, as in the process described above in relation to the figure 5 .
- the figure 9 illustrates a memory cell 900 according to an embodiment variant with respect to the figure 5 . Many elements are the same as those of the figure 5 and these elements will not be described in detail.
- the difference in the circuit of the figure 9 is that the PMOS transistor 230 is no longer present, and instead, the storage node 210 is coupled through the main current nodes of a NMOS transistor 902 to another input circuit 904.
- the transistor 902 is coupled to a data input node 906 of the memory cell 900.
- the node 906 is coupled to the supply voltage V DD by the intermediate of a circuit block 908 of the input circuit 904, and grounded via a circuit block 910 of the input circuit 904.
- the transistor 502 figure 9 is controlled by a clock signal CLK1, and the transistor 902 is controlled by a clock signal CLK2.
- Circuit blocks 908 and 910 are controlled by input data D '.
- the input data D may comprise a single data signal or several data signals.
- the input circuit 904 could correspond to the circuit of the inputs.
- Figures 7A and 7B or more generally, any logic circuit which is for example arranged to apply to the input data D at least one of the logical functions of the group comprising: a multiplexing function; a NOT function; a NON OR function; a NAND function; a NOT OR EXCLUSIVE function; an OR function an AND function; and an EXCLUSIVE OR function.
- the operation of the memory cell 900 is similar to that of the figure 5 except that, in order to generate a write current from the storage node 210, through the resistive elements 202 and 204, to the storage node 206, the transistor 902 is activated and the node 906 is coupled to the voltage supply V DD via the circuit block 908 by an appropriate value of the data signal D '.
- the remainder of the cell Memory 900 can be implemented using only five transistors.
- the figure 10 illustrates a synchronous memory device 1000 based on the circuit of the figure 9 according to an exemplary embodiment.
- the memory device 1000 could also be based on the memory cell of the figure 5 or that of the figure 8 .
- the synchronous memory device 1000 of the figure 10 is a flip-flop, and in particular a D flip-flop.
- other types of synchronous memory devices could also be implemented on the basis of the same principles.
- the storage nodes 206, 210 and the transistors 214, 216 form a master register 1001 of the memory device 1000, while the circuit 904 forms part of a slave register 1002 of the memory device 1000, coupled in series with the master register 1001 by Transceiver node 206 is further coupled to the storage node 210 of memory cell 1001 through an inverter 1004.
- the circuit 904 of the slave register 1002 is an inverter comprising a PMOS transistor 1008 coupled between the node 906 and the supply voltage V DD , and an NMOS transistor 1010 coupled between the node 906 and the ground.
- the slave register 1002 comprises another inverter consisting of a PMOS transistor 1014 and an NMOS transistor 1016 coupled in series between V DD and ground.
- the control nodes of the transistors 1014 and 1016 are coupled to the node 906, and the control nodes of the transistors 1008 and 1010 are coupled to a node 1012 between the transistors 1014 and 1016.
- the transistors 1014 and 1016 provide the input data D. on a node 1012, which is for example an output node of the synchronous memory device 1000.
- the synchronous memory device 1000 can operate as a standard flip-flop, storing data on its storage nodes 206, 210 and 906, 1012 in a volatile manner, based on input data D presented on the input of the circuit 504.
- the output of the input circuit 504 is stored on the storage node 206 and its inverse is stored on the node 210.
- the data on the storage node 210 is stored on the storage node 906, and its inverse is stored on the storage node 1012.
- data may be stored in a nonvolatile manner by programming the resistive states of memory elements 202 and 204, as previously described. This data can also be transferred to the storage nodes 206 and 210 by activating, while the clock signals CLK1 and CLK2 are low, the transistors 222 and 224 during a transfer phase as described above, and the data then become accessible on the output D 'of the flip-flop 1000 after the next rising clock edge of the clock signal CLK2.
- the signal CLK1 is brought to the high state to activate the transistor 502, and the storage node 206 is coupled to the supply voltage V DD through the input circuit 504.
- the signal CLK1 is for example again brought to the high state for activate the transistor 502, and the storage node 206 is coupled to ground via the input circuit 504.
- the inverter 1004 will then apply a relatively high voltage to the storage node 210.
- CLK2 clock can be brought high to activate the transistor 902, and the storage node 210 coupled to the supply voltage V DD through transistor 1008, based on a low state of the data signal D '.
- the figure 11 illustrates a memory network 1100 comprising an array of memory cells 1102.
- memory cells 1102 there are nine memory cells 1102 arranged in three rows and three columns. However, there could be only two rows and / or two columns, or, as shown by dotted lines in figure 11 , there could be more than three rows and / or more than three columns.
- each memory cell 1102 substantially corresponds to the memory cell of the figure 9 described above, in which the transistors 502 and 902 are coupled to corresponding bit lines BL and BL respectively.
- these two transistors are controlled by the same signal WL described in more detail below.
- the control circuit 934 of each memory cell has been replaced by common control blocks of rows and columns, as will be described now.
- a row control block 1104 provides control signals on row lines 1105 to the memory cells, a group of common row lines 1105 being provided for each row.
- each row row group 1105 comprises a word line signal WL for controlling the transistors 502, 902 of each memory cell 1102.
- this group of row lines 1105 includes, for example, the signal AZ for controlling the transistor 220 of each memory cell.
- the row control block 1104 also supplies, for example, the transfer signal TR to each memory cell on a line of rows 1106. corresponding, a row of common rows 1106 being provided for the memory cells of each row.
- the transfer signals control the transistors 222, 224 of the memory cell 200.
- a column control block 1108, receives data D V to be stored in a volatile manner by a row of memory cells during a standard write operation, and D NV data to be stored nonvolatile by each of the memory cells during a write phase of the resistive elements 202, 204 of each memory cell 1102.
- the column control block 1108 is coupled to each of the bit lines BL and BL , and includes, for each pair of bit lines BL and BL common input circuits 504, 904 for each of the memory cells.
- the programming is for example carried out by activating the word line signal WL and the signal AZ of each of the memory cells of the row to be programmed, to activate the corresponding transistors 220, 502 and 902. This creates a conduction path between the lines BL bit and BL of each column, passing through the resistive elements 202, 204 of each memory cell.
- the bit line BL or BL each column is then selectively coupled to the supply voltage V DD to generate the write current in a direction dependent on the data D NV to be programmed.
- the transfer signal TR and the signal AZ are activated as has been described in connection with the Figures 3A and 3B previously, and this operation can be performed on each of the memory cells 1102 at a time.
- the data can then be read in each memory cell row by row in a standard manner.
- data can be stored volatile in each memory cell in the same way as with RAM.
- each of the resistive elements 202 and / or 204 described herein has a structure corresponding to that of the Figure 12A or 12B .
- the resistive elements could be RedOx RAM elements, FeRAM elements, PCRAM elements, or other types of resistive elements having a programmable resistance by the direction of a flow. current.
- the figure 12A illustrates a resistive element STT 1200 having a magnetic anisotropy in the plane.
- the element 1200 is for example substantially cylindrical, but has a section which is non-circular, for example oval, which leads for example to an increase in the retention stability of the resistive states when the device is programmed.
- Element 1200 comprises lower and upper electrodes 1202 and 1204, each substantially disk-shaped, and sandwiching a number of intermediate layers therebetween.
- the intermediate layers comprise, from bottom to top, a fixed layer 1206, an oxidation barrier 1208, and a storage layer 1210.
- the oxidation barrier 1208 is for example MgO or Al x O y .
- the fixed layer 1206 and the storage layer 1210 are for example made of ferromagnetic material, such as CoFe.
- the spin direction in the fixed layer 1206 is fixed, as shown by an arrow from left to right in figure 12A .
- the spin direction could be from right to left in the fixed layer 1206.
- the spin direction in the storage layer 1210 can be changed, as represented by arrows having opposite directions in figure 12A .
- the spin direction is programmed by the direction of the write current I passed through the element, so that the spin direction in the storage layer is parallel, in other words, in the same direction , or antiparallel, in other words in the opposite direction, with respect to the fixed layer 1206.
- the figure 12B illustrates a resistive element STT 1220 having a magnetic anisotropy perpendicular to the plane.
- a resistive element may for example be programmed by a lower write current I than for the element 1200 for a given size and / or for a given volume of storage layer.
- Such an element is therefore for example used in the memory cell 500 of the figure 5 where a relatively low write current is desirable.
- the element 1220 is substantially cylindrical, and has for example a section which is circular.
- Element 1220 includes lower and upper electrodes 1222 and 1224, each substantially disk-shaped and sandwiching a number of intermediate layers.
- the intermediate layers comprise, from bottom to top, a fixed layer 1226, an oxidation barrier 1228, and a storage layer 1230. These layers are similar to the corresponding layers 1206, 1208 and 1210 of the element 1200, except that the fixed layer 1226 and the storage layer 1230 have anisotropy perpendicular to the plane, as represented by the vertical arrows in the layers 1226 and 1230 of the figure 12B .
- the fixed layer 1226 is illustrated as having a spin direction from bottom to top in figure 12B but of course, in alternative embodiments, this spin direction could be from top to bottom.
- each of the resistive elements 202, 204 described here their orientations may for example be chosen so as to minimize the level of write current that allows them to be programmed.
- a low write current may be present when each element has its lower electrode 1202, 1222 connected to the corresponding storage node 206, 210, or the opposite may be true as well.
- the supply voltage V DD in the various embodiments could have any level, for example between 1 and 3 V, and rather than being 0 V, the ground voltage can also be considered as a supply voltage that could be at any level, such as a negative level.
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Description
La présente demande de brevet revendique la priorité de la demande de brevet français
La présente description concerne une cellule mémoire et un procédé de mémorisation non volatile d'une valeur de données dans une cellule mémoire. En particulier, la présente description concerne une cellule mémoire et un procédé comprenant un ou plusieurs éléments résistifs pouvant être programmés par la direction d'un courant.The present disclosure relates to a memory cell and a method for nonvolatile storage of a data value in a memory cell. In particular, the present description relates to a memory cell and a method comprising one or more resistive elements that can be programmed by the direction of a current.
On a déjà proposé d'utiliser des éléments résistifs programmables dans des cellules mémoires pour assurer une mémorisation de données non volatile. De tels éléments résistifs sont programmables pour prendre l'un d'une pluralité d'états résistifs différents. L'état résistif programmé est conservé même lorsqu'une tension d'alimentation de la cellule mémoire est déconnectée, et par conséquent des données peuvent être mémorisées par de tels éléments de façon non volatile.It has already been proposed to use programmable resistive elements in memory cells to ensure nonvolatile data storage. Such resistive elements are programmable to take one of a plurality of different resistive states. The programmed resistive state is maintained even when a supply voltage of the memory cell is disconnected, and therefore data may be stored by such elements in a non-volatile manner.
Divers types d'éléments résistifs ont été proposés, dont certains peuvent être programmés par la direction d'un courant qu'on fait passer dans les éléments résistifs. Un exemple d'un tel élément résistif programmable par un courant est un élément STT (à couple de transfert de spin), qui est basé sur des jonctions tunnel magnétiques (MTJ).Various types of resistive elements have been proposed, some of which may be programmed by the direction of a current passed through the resistive elements. An example of such a resistive element programmable by a current is an STT (spin transfer torque) element, which is based on magnetic tunnel junctions (MTJ).
En raison au moins en partie des transistors utilisés pour programmer les états résistifs, les cellules mémoires basées sur des éléments résistifs programmables ont tendance à être moins compactes que d'autres types de cellules mémoires comme celles de mémoire RAM (mémoire à accès aléatoire) . Il existe un besoin général dans la technique d'une cellule mémoire basée sur des éléments résistifs programmables ayant une surface réduite.Because at least some of the transistors used to program the resistive states, the memory cells based on programmable resistive elements tend to be less compact than other types of memory cells such as those of random access memory (RAM). There is a general need in the art of a memory cell based on programmable resistive elements having a small area.
La demande de brevet US publiée sous le numéro
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Un objet de modes de réalisation de la présente description est de répondre au moins partiellement à un ou plusieurs besoins de l'art antérieur.An object of embodiments of the present description is to at least partially meet one or more needs of the prior art.
Selon un aspect, on prévoit une cellule mémoire comprenant : des premier et deuxième éléments résistifs, au moins l'un d'eux étant programmable pour prendre l'un d'au moins deux états résistifs, une valeur de donnée étant représentée par les résistances relatives des premier et deuxième éléments résistifs, le premier élément résistif étant couplé entre un premier noeud de mémorisation et un premier noeud intermédiaire, le deuxième élément résistif étant couplé entre un deuxième noeud de mémorisation et un deuxième noeud intermédiaire ; un premier transistor couplé entre le premier noeud de mémorisation et une première tension d'alimentation ; un deuxième transistor couplé entre le deuxième noeud de mémorisation et la première tension d'alimentation, un noeud de commande du premier transistor étant couplé au deuxième noeud de mémorisation et un noeud de commande du deuxième transistor étant couplé au premier noeud de mémorisation ; un troisième transistor couplé entre les premier et deuxième noeuds intermédiaires ; un quatrième transistor couplé par ses noeuds de courant principaux entre le premier noeud de mémorisation et un noeud d'entrée de données ; et un circuit de commande agencé, pendant une phase d'écriture, pour activer les troisième et quatrième transistors et pour coupler le noeud d'entrée de données à une deuxième tension d'alimentation par l'intermédiaire d'un premier bloc de circuit pour générer un courant dans une première direction à travers les premier et deuxième éléments résistifs pour programmer l'état résistif d'au moins l'un des éléments.According to one aspect, there is provided a memory cell comprising: first and second resistive elements, at least one of them being programmable to take one of at least two resistive states, a data value being represented by the resistors relative first and second resistive elements, the first resistive element being coupled between a first storage node and a first intermediate node, the second resistive element being coupled between a second storage node and a second intermediate node; a first transistor coupled between the first storage node and a first supply voltage; a second transistor coupled between the second storage node and the first supply voltage, a control node of the first transistor coupled to the second storage node and a control node of the second transistor coupled to the first storage node; a third transistor coupled between the first and second intermediate nodes; a fourth transistor coupled by its main current nodes between the first storage node and a data input node; and a control circuit arranged, during a writing phase, to activate the third and fourth transistors and to couple the data input node to a second supply voltage through a first circuit block to generate a current in a first direction through the first and second elements resistive for programming the resistive state of at least one of the elements.
Selon un mode de réalisation, le premier bloc de circuit comprend au moins un transistor couplé entre le noeud d'entrée de données et la deuxième tension d'alimentation et contrôlé par des données d'entrée de la cellule mémoire.According to one embodiment, the first circuit block comprises at least one transistor coupled between the data input node and the second supply voltage and controlled by input data of the memory cell.
Selon un mode de réalisation, la cellule mémoire comprend en outre un deuxième bloc de circuit comprenant au moins un transistor couplé entre le noeud d'entrée de données et la première tension d'alimentation et contrôlé par les données d'entrée de la cellule mémoire.According to one embodiment, the memory cell further comprises a second circuit block comprising at least one transistor coupled between the data input node and the first supply voltage and controlled by the input data of the memory cell. .
Selon un mode de réalisation, les premier et deuxième blocs de circuit sont agencés pour appliquer à la donnée d'entrée au moins l'une des fonctions logiques du groupe comprenant : une fonction de multiplexage ; une fonction NON ; une fonction NON OU ; une fonction NON ET ; une fonction NON OU EXCLUSIF ; une fonction OU ; une fonction ET ; et une fonction OU EXCLUSIF.According to one embodiment, the first and second circuit blocks are arranged to apply to the input data at least one of the logical functions of the group comprising: a multiplexing function; a NOT function; a NON OR function; a NAND function; a NOT OR EXCLUSIVE function; an OR function an AND function; and an EXCLUSIVE OR function.
Selon un mode de réalisation, la cellule mémoire comprend en outre un cinquième transistor couplé entre le deuxième noeud de mémorisation et la deuxième tension d'alimentation, le circuit de commande étant en outre agencé, pendant une autre phase d'écriture, pour activer les troisième et cinquième transistors pour générer un courant de programmation dans une deuxième direction dans les premier et deuxième éléments résistifs pour programmer l'état résistif d'au moins l'un des éléments.According to one embodiment, the memory cell further comprises a fifth transistor coupled between the second storage node and the second supply voltage, the control circuit being furthermore arranged, during another write phase, to activate the third and fifth transistors for generating a programming current in a second direction in the first and second resistive elements for programming the resistive state of at least one of the elements.
Selon un mode de réalisation, la cellule mémoire comprend en outre un sixième transistor couplé entre le deuxième noeud de mémorisation et un autre noeud d'entrée de données, le circuit de commande étant en outre agencé, pendant une autre phase d'écriture, pour activer les troisième et sixième transistors et pour coupler l'autre noeud d'entrée de données à la deuxième tension d'alimentation par l'intermédiaire d'un autre bloc de circuit pour générer un courant de programmation dans une deuxième direction dans les premier et deuxième éléments résistifs pour programmer l'état résistif d'au moins l'un des éléments.According to one embodiment, the memory cell further comprises a sixth transistor coupled between the second storage node and another data input node, the control circuit being further arranged, for another write phase, to activate the third and sixth transistors and to couple the other data input node to the second power supply voltage via another circuit block to generate a programming current in a second direction in the first and second resistive elements for programming the resistive state of at least one of the elements.
Selon un mode de réalisation, la cellule mémoire comprend en outre un inverseur couplé entre le premier noeud de mémorisation et le deuxième noeud de mémorisation, le circuit de commande étant en outre agencé, pendant une autre phase d'écriture, pour activer les troisième et quatrième transistors et pour coupler le noeud d'entrée de données à la première tension d'alimentation par l'intermédiaire du deuxième bloc de circuit pour générer un courant de programmation dans une deuxième direction dans les premier et deuxième éléments résistifs pour programmer l'état résistif d'au moins l'un des éléments.According to one embodiment, the memory cell further comprises an inverter coupled between the first storage node and the second storage node, the control circuit being furthermore arranged, during another write phase, to activate the third and fourth transistors and for coupling the data input node to the first power supply voltage via the second circuit block to generate a programming current in a second direction in the first and second resistive elements for programming the state resistive of at least one of the elements.
Selon un mode de réalisation, chacun des premier et deuxième transistors est connecté à la première tension d'alimentation.According to one embodiment, each of the first and second transistors is connected to the first supply voltage.
Selon un mode de réalisation, au moins l'un des premier et deuxième éléments résistifs est l'un des éléments suivants : un élément à couple de transfert de spin ayant une anisotropie dans le plan ; un élément à couple de transfert de spin ayant une anisotropie perpendiculaire au plan ; un élément à oxydoréduction (RedOx) ; un élément ferroélectrique ; et un élément à changement de phase.According to one embodiment, at least one of the first and second resistive elements is one of the following: a spin transfer torque element having anisotropy in the plane; a spin transfer torque element having anisotropy perpendicular to the plane; a redox element (RedOx); a ferroelectric element; and a phase change element.
Selon un mode de réalisation, chacun des premier et deuxième transistors comprend un noeud de substrat, et le circuit de commande est en outre agencé pour coupler le noeud de substrat d'au moins l'un des premier et deuxième transistors à une troisième tension d'alimentation différente de la première tension d'alimentation pendant que le noeud d'entrée de données est couplé à la deuxième tension d'alimentation.According to one embodiment, each of the first and second transistors comprises a substrate node, and the control circuit is further arranged to couple the substrate node of at least one of the first and second transistors to a third voltage. supply different from the first supply voltage while the data input node is coupled to the second supply voltage.
Selon un mode de réalisation, la cellule mémoire comprend en outre un septième transistor couplé entre le premier noeud intermédiaire et la deuxième tension d'alimentation ; et un huitième transistor couplé entre le deuxième noeud intermédiaire et la deuxième tension d'alimentation, les septième et huitième transistors étant par exemple adaptés à avoir une tension de seuil inférieure à celle des premier et deuxième transistors.According to one embodiment, the memory cell further comprises a seventh transistor coupled between the first intermediate node and the second supply voltage; and an eighth transistor coupled between the second intermediate node and the second supply voltage, the seventh and eighth transistors being for example adapted to have a threshold voltage lower than that of the first and second transistors.
Selon un autre aspect, on prévoit un dispositif mémoire comprenant : un réseau des cellules mémoires susmentionnées, les noeuds d'entrée de données des cellules mémoires étant couplés à des premières lignes de bits du dispositif mémoire.In another aspect, there is provided a memory device comprising: an array of the aforementioned memory cells, the data input nodes of the memory cells being coupled to first bit lines of the memory device.
Selon un autre aspect, on prévoit un dispositif mémoire synchrone comprenant la cellule mémoire susmentionnée et une autre cellule mémoire couplée en série avec la cellule mémoire, l'autre cellule mémoire comprenant deux inverseurs couplés de façon croisée.According to another aspect, there is provided a synchronous memory device comprising the aforementioned memory cell and another memory cell coupled in series with the memory cell, the other memory cell comprising two inverters cross-coupled.
Selon un autre aspect, on prévoit un procédé de mémorisation non volatile d'une valeur de donnée dans une cellule mémoire, la cellule mémoire comprenant des premier et deuxième éléments résistifs, dont au moins l'un est programmable pour prendre l'un d'au moins deux états résistifs, une valeur de donnée étant représentée par les résistances relatives des premier et deuxième éléments résistifs, le premier élément résistif étant couplé entre un premier noeud de mémorisation et un premier noeud intermédiaire, le deuxième élément résistif étant couplé entre un deuxième noeud de mémorisation et un deuxième noeud intermédiaire ; un premier transistor couplé entre le premier noeud de mémorisation et une première tension d'alimentation ; un deuxième transistor couplé entre le deuxième noeud de mémorisation et la première tension d'alimentation, un noeud de commande du premier transistor étant couplé au deuxième noeud de mémorisation et un noeud de commande du deuxième transistor étant couplé au premier noeud de mémorisation ; un troisième transistor couplé entre les premier et deuxième noeuds intermédiaires ; un quatrième transistor couplé par ses noeuds de courant principaux entre le premier noeud de mémorisation et un noeud d'entrée de données, le procédé comprenant : activer les troisième et quatrième transistors ; coupler le noeud d'entrée de données à une deuxième tension d'alimentation par l'intermédiaire d'un premier bloc de circuit d'entrée pendant que les troisième et quatrième transistors sont activés pour générer un courant de programmation dans une première direction dans les premier et deuxième éléments résistifs pour programmer l'état résistif d'au moins l'un des éléments.According to another aspect, there is provided a method for non-volatile storage of a data value in a memory cell, the memory cell comprising first and second resistive elements, at least one of which is programmable to take one of at least two resistive states, a data value being represented by the relative resistances of the first and second resistive elements, the first resistive element being coupled between a first storage node and a first intermediate node, the second resistive element being coupled between a second resistive element storage node and a second intermediate node; a first transistor coupled between the first storage node and a first supply voltage; a second transistor coupled between the second storage node and the first supply voltage, a control node of the first transistor coupled to the second storage node and a control node of the second transistor coupled to the first storage node; a third transistor coupled between the first and second intermediate nodes; a fourth transistor coupled by its main current nodes between the first storage node and a data input node, the method comprising: enabling the third and fourth transistors; coupling the data input node to a second supply voltage through a first input circuit block while the third and fourth transistors are activated to generate a programming current in a first direction in the first input circuit blocks; first and second resistive elements for programming the resistive state of at least one of the elements.
Les caractéristiques et avantages susmentionnés, et d'autres, apparaîtront clairement avec la description détaillée suivante de modes de réalisation, faite à titre d'illustration et non de limitation, en référence aux dessins joints, dans lesquels :
- la
figure 1 illustre schématiquement une cellule mémoire qui a été proposée ; - la
figure 2 illustre schématiquement une cellule mémoire selon un exemple de réalisation de la présente description ne tombant pas sous la protection des revendications jointes en annexe; - les
figures 3A et 3B sont des chronogrammes représentant des signaux dans le circuit de lafigure 2 pendant une phase de transfert de données selon un exemple de réalisation de la présente description ; - les
figures 4A et 4B sont des chronogrammes représentant des signaux dans le circuit de lafigure 2 pendant une phase d'écriture selon un exemple de réalisation de la présente description ; - la
figure 5 illustre schématiquement une cellule mémoire selon un autre exemple de réalisation de la présente description ; - les
figures 6A et 6B sont des chronogrammes représentant des signaux dans la cellule mémoire de lafigure 5 pendant une phase d'écriture selon un exemple de réalisation de la présente description ; - les
figures 7A et 7B illustrent schématiquement plus en détail des circuits de la cellule mémoire de lafigure 5 selon des exemples de réalisation de la présente description ; - la
figure 8 illustre schématiquement une cellule mémoire selon un autre exemple de réalisation de la présente description ; - la
figure 9 illustre schématiquement une cellule mémoire selon encore un autre exemple de réalisation de la présente description ; - la
figure 10 illustre schématiquement un dispositif mémoire synchrone selon un exemple de réalisation de la présente description ; - la
figure 11 illustre schématiquement un réseau mémoire selon un exemple de réalisation de la présente description ; et - les
figures 12A et 12B illustrent des éléments résistifs basés sur des jonctions tunnel magnétiques selon des exemples de réalisation de la présente description.
- the
figure 1 schematically illustrates a memory cell that has been proposed; - the
figure 2 schematically illustrates a memory cell according to an exemplary embodiment of the present description not falling under the protection of the appended claims; - the
Figures 3A and 3B are chronograms representing signals in the circuit of thefigure 2 during a data transfer phase according to an exemplary embodiment of the present description; - the
Figures 4A and 4B are chronograms representing signals in the circuit of thefigure 2 during a write phase according to an exemplary embodiment of the present description; - the
figure 5 schematically illustrates a memory cell according to another embodiment of the present description; - the
Figures 6A and 6B are timing diagrams representing signals in the memory cell of thefigure 5 during a write phase according to an exemplary embodiment of the present description; - the
Figures 7A and 7B schematically illustrate in more detail circuits of the memory cell of thefigure 5 according to exemplary embodiments of the present description; - the
figure 8 schematically illustrates a memory cell according to another embodiment of the present description; - the
figure 9 schematically illustrates a memory cell according to yet another embodiment of the present description; - the
figure 10 schematically illustrates a synchronous memory device according to an exemplary embodiment of the present description; - the
figure 11 schematically illustrates a memory network according to an exemplary embodiment of the present description; and - the
Figures 12A and 12B illustrate resistive elements based on magnetic tunnel junctions according to embodiments of the present description.
Dans la description suivante, le terme "connecté" est utilisé pour désigner une connexion directe entre un élément et un autre, tandis que le terme "couplé" implique que la connexion entre les deux éléments peut être faite directement, ou via un élément intermédiaire, comme un transistor, une résistance ou un autre composant.In the following description, the term "connected" is used to designate a direct connection between one element and another, while the term "coupled" implies that the connection between the two elements can be made directly, or via an intermediate element, like a transistor, a resistor or some other component.
La
La bascule 100 représentée en
Un transistor MN5 est couplé entre le noeud intermédiaire 104 et la tension d'alimentation Vdd, et un transistor MN6 est couplé entre le noeud intermédiaire 104 et la masse. En outre, un transistor MN3 est couplé entre le noeud intermédiaire 106 et la tension d'alimentation Vdd, et un transistor MN4 est couplé entre le noeud intermédiaire 106 et la masse. Un transistor MN7 est couplé entre le noeud intermédiaire 102 et la masse. Les transistors MN3 à MN6 permettent le passage d'un courant dans les éléments résistifs MTJ1 et MTJ0 dans une direction ou dans l'autre afin de programmer les états résistifs des dispositifs MTJ. Pendant cette phase de programmation, le transistor MN7 est utilisé pour déconnecter le noeud 102 de la masse.An MN5 transistor is coupled between the
Une paire de portes NOR et un inverseur sur le côté gauche de la
Un inconvénient du circuit de la
La
La cellule mémoire 200 comprend des éléments résistifs 202 et 204, chacun d'eux pouvant être programmé pour prendre l'un d'une pluralité d'états résistifs. Les éléments résistifs 202 et 204 peuvent être d'un type quelconque d'élément à commutation de résistance pour lequel la résistance est programmable par la direction d'un courant qu'on fait passer dedans. Par exemple, comme on va le décrire plus en détail dans la suite en référence aux
Quel que soit le type d'élément résistif, un bit de donnée est par exemple mémorisé dans la cellule mémoire de façon non volatile en mettant l'un des éléments à une résistance relativement élevée (Rmax), et l'autre à une résistance relativement basse (Rmin). Dans l'exemple de la
Le bit de donnée non volatile représenté par les éléments résistifs 202, 204 dépend duquel des éléments résistifs a la résistance Rmax ou Rmin, en d'autres termes, dépend des résistances relatives. Les éléments résistifs 202, 204 sont par exemple sélectionnés de telle sorte que Rmax soit toujours notablement supérieure à Rmin, par exemple supérieure d'au moins 20 pourcent. En général, le rapport entre la résistance Rmax et la résistance Rmin est par exemple compris entre 1,2 et 10000. Rmin est par exemple dans la région des 2 kilo-ohms ou moins, et Rmax est par exemple dans la région des 6 kilo-ohms ou plus, bien que d'autres valeurs soient possibles.The non-volatile data bit represented by the
Il sera clair pour l'homme de l'art que dans certains modes de réalisation, plutôt que les deux éléments résistifs 202, 204 soient programmables, un seul soit programmable. Dans un tel cas, l'autre élément résistif a par exemple une résistance fixe à un niveau intermédiaire environ à mi-chemin entre Rmin et Rmax, par exemple égal avec une tolérance de 10 pourcent, à (Rmin+(Rmax-Rmin)/2). Par exemple, l'un des éléments résistifs 202, 204 pourrait correspondre à une résistance de valeur fixe. A titre de variante, l'un des éléments résistifs 202, 204 pourrait être constitué de deux éléments résistifs programmables couplés en parallèle et ayant des orientations opposées, de sorte quel que soit le sens dans lequel chaque élément est programmé, la valeur de résistance reste relativement constante au niveau intermédiaire.It will be clear to those skilled in the art that in some embodiments, rather than the two
L'élément résistif 202 est couplé entre un noeud de mémorisation 206 et un noeud intermédiaire 208. L'élément résistif 204 est couplé entre un noeud de mémorisation 210 et un noeud intermédiaire 212. Les noeuds de mémorisation 206 et 210 mémorisent des tensions Q et
Les noeuds intermédiaires 208 et 212 sont couplés entre eux par l'intermédiaire des noeuds de courant principaux d'un transistor NMOS 220. Le transistor 220 reçoit sur son noeud de commande un signal AZ décrit plus en détail ci-après.The
Le noeud 208 est en outre couplé à une tension d'alimentation VDD par l'intermédiaire des noeuds de courant principaux d'un transistor MOS à canal P (PMOS) 222. De façon similaire, le noeud 212 est couplé à la tension d'alimentation VDD par l'intermédiaire des noeuds de courant principaux d'un transistor PMOS 224. Les noeuds de commande des transistors PMOS 222 et 224 sont couplés ensemble à un signal de transfert TR décrit plus en détail ci-après.The
Le noeud de mémorisation 206 est en outre couplé à la tension d'alimentation VDD par l'intermédiaire des noeuds de courant principaux d'un transistor PMOS 226, et à la masse par l'intermédiaire des noeuds de courant principaux d'un transistor NMOS 228. Les transistors 226 et 228 reçoivent sur leurs noeuds de commande des signaux d'écriture WP1 et WN1 respectivement. De façon similaire, le noeud de mémorisation 210 est couplé à la tension d'alimentation VDD par l'intermédiaire des noeuds de courant principaux d'un transistor PMOS 230, et à la masse par l'intermédiaire des noeuds de courant principaux d'un transistor NMOS 232. Les transistors 230 et 232 reçoivent sur leurs noeuds de commande des signaux d'écriture WP2 et WN2 respectivement.The
La
Dans la bascule 100 de la
Les tensions de seuil des transistors PMOS 222, 224 et/ou 226, 230 sont choisies de façon à être inférieures à celles des transistors NMOS 214, 216, 228, 232 de sorte que lorsqu'ils sont dans l'état non conducteur, le courant de fuite dans les transistors 222, 224 et/ou 226, 230 est supérieur à celui dans les transistors 214, 216, 228, 232, maintenant ainsi le noeud correspondant 206 ou 210 à une tension suffisamment haute pour être vue comme un état logique haut. En d'autres termes, le courant de fuite IoffP passant dans le transistor PMOS 222, 224 et/ou 226, 230 lorsqu'une tension de niveau haut est appliquée aux noeuds de grille correspondants est supérieur au courant de fuite IoffN passant dans le transistor NMOS correspondant 214, 216, 228 ou 232 lorsqu'une tension de niveau bas est appliquée sur son noeud de grille.The threshold voltages of the
Les tensions de seuil particulières vont dépendre de la technologie utilisée. À titre d'exemple, les tensions de seuil des transistors PMOS 222, 224, et/ou 226, 230 sont choisies de façon à être dans la plage de 0,3 à 0,5 V, alors que les tensions de seuil des transistors NMOS 214, 216, 228, 232 sont la plage de 0,4 à 0,6 V. Dans tous les cas, le rapport I0ffp/IOffn est sélectionné par exemple pour être supérieur à 25, et de préférence supérieur à 100.The particular threshold voltages will depend on the technology used. By way of example, the threshold voltages of the
On va maintenant décrire plus en détail le fonctionnement du circuit de la
D'abord, on notera que, contrairement à la bascule de la
Les
La phase de transfert correspond à une opération consistant à transférer la donnée représentée par les états résistifs programmés des éléments résistifs 202 et 204 vers les noeuds de mémorisation 206, 210. Ainsi, la donnée est transformée d'une représentation par l'état résistif programmé en une représentation par des niveaux de tension sur les noeuds de mémorisation 206 et 210.The transfer phase corresponds to an operation consisting in transferring the data represented by the programmed resistive states of the
Ainsi, la phase de transfert implique d'établir les niveaux des tensions Q et
La
Le signal de transfert TR est par exemple initialement haut, de sorte que les transistors 222 et 224 sont non-conducteurs. Le signal AZ est par exemple initialement bas, de sorte que le transistor 220 est non conducteur.The transfer signal TR is for example initially high, so that the
Le signal de phase de transfert TPH, qui est par exemple initialement bas, est activé comme cela est représenté par un front montant 302, déclenchant peu de temps après un front descendant du signal de transfert TR, et un front montant du signal AZ, par exemple peu de temps après le front descendant du signal de transfert TR. Ainsi, les transistors 220, 222 et 224 de la
Toutefois, en raison de la différence entre les résistances des éléments résistifs 202 et 204, le courant dans la branche de gauche est inférieur au courant dans la branche de droite. Ainsi, ces courants par exemple provoquent la descente de la tension sur le noeud de mémorisation 206 et son établissement à un niveau V1 inférieur à un niveau de métastabilité M, et la montée de la tension sur le noeud de mémorisation 210 jusqu'à un niveau V2 supérieur au niveau de métastabilité M. Le niveau de métastabilité M est un niveau de tension théorique situé environ à mi-chemin entre les états de tension haut et bas, représentant le niveau à partir duquel il y aurait une probabilité égale que Q bascule vers l'état haut ou vers l'état bas. L'activation du signal AZ pour rendre conducteur le transistor 220 a pour effet d'accélérer la descente du niveau de tension Q, et la montée du niveau de tension
Le signal AZ est ensuite amené à l'état bas, et le signal de transfert TR est amené de nouveau à l'état haut sur un front montant 304, de sorte que les niveaux Q et
La
Les
La phase d'écriture implique le passage d'un courant dans chacun des éléments résistifs 202, 204 par l'intermédiaire du transistor 220, soit dans la direction allant du noeud de mémorisation 206 vers le noeud de mémorisation 210, soit dans la direction opposée. Les éléments résistifs 202 et 204 sont orientés de telle sorte que, pour une direction donnée du courant, ils vont être programmés de façon à avoir des résistances opposées. En particulier, chaque élément résistif 202, 204 peut être orienté dans l'une de deux façons entre le noeud de mémorisation 206, 210 correspondant et le noeud intermédiaire 208, 212 correspondant. Dans le cas d'un élément STT, l'orientation est déterminée par l'ordre d'une couche fixe et d'une couche de mémorisation, comme cela va être décrit plus en détail ci-après. Les éléments 202, 204 sont tous deux par exemple orientés de la même façon entre ces noeuds correspondants, par exemple chacun ayant sa couche fixe située la plus proche du noeud de mémorisation 206, 210 correspondant, de sorte qu'ils ont des orientations opposées par rapport à un courant d'écriture passant du noeud de mémorisation 206 vers le noeud de mémorisation 210 ou vice versa.The write phase involves the passage of a current in each of the
Comme cela est illustré en
Le signal de données DNV sur la ligne d'entrée 236 du circuit de commande 234 est par exemple d'abord mis à la valeur qui doit être programmée dans la cellule mémoire. Dans l'exemple de la
Le signal de phase d'écriture WPH sur la ligne d'entrée 238 du circuit de commande 234 passe ensuite à l'état haut sur un front montant 404, lançant le début de la phase d'écriture. Cela déclenche, peu de temps après, un front montant du signal AZ, de sorte que le transistor 220 est activé, couplant entre eux les noeuds 208 et 212. En outre, peu de temps après, les signaux WP1, WN1, WP2 et WN2 sont mis à des valeurs appropriées pour provoquer le passage d'un courant dans les éléments résistifs 202 et 204 dans une direction qui va programmer leurs résistances conformément à la valeur de donnée "1" logique qui doit être programmée. Dans l'exemple de la
Après que le courant a été appliqué pendant un temps suffisant pour établir les états résistifs des éléments 202 et 204, par exemple pendant une durée tW comprise entre 0,1 ns et 20 ns, le signal WP1 est amené de nouveau à l'état haut, et le signal WN2 est amené à l'état bas, arrêtant le courant d'écriture. Les signaux AZ et WPH sont ensuite par exemple amenés à l'état bas, ce qui termine la phase d'écriture.After the current has been applied for a time sufficient to establish the resistive states of the
La
Les transistors 220 et 226 à 232 sont par exemple dimensionnés de telle sorte que le courant d'écriture généré par l'activation des transistors 226, 220 et 232, ou par l'activation des transistors 230, 220 et 228, soit suffisamment élevé pour programmer les états résistifs des éléments 202 et 204. En fonction du type et des dimensions des éléments résistifs 202, 204, un tel courant de programmation minimum serait par exemple de l'ordre de 20 µA à 1,5 mA. Au contraire, les transistors 214, 216 et 222, 224 sont par exemple dimensionnés de telle sorte que, pendant une phase de transfert lorsque le signal de transfert TR est activé, le niveau du courant passant dans les éléments résistifs 202 et 204 soit inférieur à celui nécessaire pour programmer leurs états résistifs, par exemple un niveau inférieur de 10 à 90 pourcent par rapport au courant d'écriture correspondant.
En référence à la
La
Une différence dans la cellule mémoire 500 est que les transistors 226, 228 et 232 ont été supprimés, laissant seulement un unique transistor 230 dédié à la génération du courant d'écriture. Un transistor NMOS supplémentaire 502 est couplé par ses noeuds de courant principaux entre le noeud de mémorisation 206 et un circuit d'entrée 504. En particulier, le transistor 502 est couplé à un noeud d'entrée de données 506 de la cellule mémoire. Le noeud 506 est couplé à la tension d'alimentation VDD par l'intermédiaire d'un bloc de circuit 508 du circuit d'entrée 504, et à la masse par l'intermédiaire d'un bloc de circuit 510 du circuit d'entrée 504. Le transistor 502 est par exemple contrôlé par un signal d'horloge CLK. Les blocs de circuit 508 et 510 sont contrôlés par des données d'entrée D au niveau d'une entrée 512. Comme cela apparaîtra clairement d'après la description qui suit, les données d'entrée D peuvent comprendre un unique signal de données ou plusieurs signaux de données pour contrôler les blocs de circuits 508, 510.A difference in
En outre, des noeuds de tension de substrat des transistors 214 et 216 sont illustrés en
Une phase de transfert peut être mise en oeuvre dans le circuit 500 de la même façon que cela a été décrit précédemment en relation avec les
Une phase d'écriture des éléments résistifs 202 et 204 est mise en oeuvre en utilisant le transistor PMOS 230 ou le circuit d'entrée 504, en fonction de la direction du courant d'écriture à appliquer. En particulier, le circuit d'entrée 504 correspond à un dispositif de type CMOS typique comprenant, dans le bloc de circuit 508, un ou plusieurs transistors PMOS couplés à la tension d'alimentation VDD, et, dans le bloc de circuit 510, un ou plusieurs transistors NMOS, couplés à la masse. Par exemple, le circuit d'entrée 504 correspond à un inverseur, un multiplexeur, une porte NON OU, une porte NON ET, ou un autre circuit logique.A write phase of the
Afin de programmer les éléments résistifs 202, 204 avec un courant d'écriture circulant à partir du noeud de mémorisation 206 vers le noeud de mémorisation 210, le transistor 502 est activé, et le bloc de circuit 508 est aussi activé par une valeur appropriée du signal de données D pour coupler le noeud intermédiaire 506 à la tension d'alimentation VDD. Le chemin entre le noeud de mémorisation 210 et la masse est par exemple assuré par le transistor 216.In order to program the
Afin de programmer les éléments résistifs 202, 204 avec un courant d'écriture passant du noeud de mémorisation 210 vers le noeud de mémorisation 206, le transistor 230 est activé. Le chemin entre le noeud de mémorisation 206 et la masse est soit assuré uniquement par le transistor 214, soit par le transistor 214 et en plus par l'activation du transistor 502 et du bloc de circuit 510 par une donnée d'entrée D appropriée sur l'entrée 512.In order to program the
Le circuit d'entrée 504, en plus de fournir un état de tension au noeud d'entrée de données 506 de la cellule mémoire pendant une phase d'écriture, sert aussi par exemple comme interface d'entrée ou de sortie de la cellule mémoire 500. En particulier, le circuit d'entrée 504 par exemple applique un signal au noeud d'entrée de données 506 pour programmer les états de tension Q et
En plus ou à la place, le circuit d'entrée 504 peut être agencé pour lire l'état de tension Q sur le noeud de mémorisation 206, et le circuit d'entrée 504 par exemple fonctionne en plus comme circuit de sortie de la cellule mémoire 500.In addition or instead, the
Avantageusement, en utilisant le circuit d'entrée 504 et le transistor 502 pour appliquer un niveau de tension au noeud de mémorisation 206 ou 210 pendant une phase d'écriture des éléments résistifs 202, 204, le reste de la cellule mémoire 500 de la
On va maintenant décrire plus en détail le fonctionnement de la cellule mémoire 500 pendant une phase d'écriture, en référence aux
Les
Dans l'exemple de la
Dans l'exemple de la
La commande des tensions de substrat VBULK1 et VBULK2 des transistors 214 et 216 peut être utilisée pour augmenter le courant d'écriture, comme on va le décrire maintenant.Controlling substrate voltages V BULK1 and V BULK2 of
En faisant de nouveau référence aux
Dans l'exemple de la
Dans l'exemple de la
Les
La
La
De façon plus générale, les blocs de circuit 508 et 510 du circuit d'entrée 504 sont par exemple agencés pour appliquer à la donnée d'entrée D au moins l'une des fonctions logiques du groupe comprenant : une fonction de multiplexage ; une fonction NON ; une fonction NON OU ; une fonction NON ET ; une fonction NON OU EXCLUSIF ; une fonction OU ; une fonction ET ; et une fonction OU EXCLUSIF.More generally, the circuit blocks 508 and 510 of the
La
Il apparaîtra clairement à l'homme de l'art que le fonctionnement de la cellule mémoire de la
La
Comme dans le circuit d'entrée 504, le circuit d'entrée 904 pourrait correspondre au circuit des
Le fonctionnement de la cellule mémoire 900 est similaire à celui de la
Ainsi, en utilisant à la fois les transistors 502, 902 et les circuits d'entrée 504, 904 pour appliquer des tensions aux noeuds de mémorisation 206 et 210 pendant des phases d'écriture des éléments résistifs 202, 204, le reste de la cellule mémoire 900 peut être mis en oeuvre en utilisant seulement cinq transistors.Thus, by using both
La
Les noeuds de mémorisation 206, 210 et les transistors 214, 216 forment un registre maître 1001 du dispositif mémoire 1000, tandis que le circuit 904 fait partie d'un registre esclave 1002 du dispositif mémoire 1000, couplé en série avec le registre maître 1001 par l'intermédiaire du transistor 902. Le noeud de mémorisation 206 est en outre couplé au noeud de mémorisation 210 de la cellule mémoire 1001 par l'intermédiaire d'un inverseur 1004.The
Le circuit 904 du registre esclave 1002 est un inverseur comprenant un transistor PMOS 1008 couplé entre le noeud 906 et la tension d'alimentation VDD, et un transistor NMOS 1010 couplé entre le noeud 906 et la masse. Le registre esclave 1002 comprend un autre inverseur constitué d'un transistor PMOS 1014 et d'un transistor NMOS 1016 couplés en série entre VDD et la masse. Les noeuds de commande des transistors 1014 et 1016 sont couplés au noeud 906, et les noeuds de commande des transistors 1008 et 1010 sont couplés à un noeud 1012 entre les transistors 1014 et 1016. Les transistors 1014 et 1016 fournissent la donnée d'entrée D' sur un noeud 1012, qui est par exemple un noeud de sortie du dispositif mémoire synchrone 1000.The
En fonctionnement, quel que soient les états résistifs programmés des éléments résistifs 202 et 204, le dispositif mémoire synchrone 1000 peut opérer comme une bascule standard, mémorisant des données sur ses noeuds de mémorisation 206, 210 et 906, 1012 de façon volatile, sur la base de données d'entrée D présentées sur l'entrée du circuit 504. En particulier, sur un front montant de l'horloge CLK1, la sortie du circuit d'entrée 504 est mémorisée sur le noeud de mémorisation 206 et son inverse est mémorisé sur le noeud 210. Ensuite, sur un front montant du signal d'horloge CLK2, la donnée sur le noeud de mémorisation 210 est mémorisée sur le noeud de mémorisation 906, et son inverse est mémorisé sur le noeud de mémorisation 1012.In operation, regardless of the programmed resistive states of the
En outre, des données peuvent être mémorisées de façon non volatile en programmant les états résistifs des éléments mémoire 202 et 204, comme cela a été décrit précédemment. Ces données peuvent aussi être transférées vers les noeuds de mémorisation 206 et 210 en activant, pendant que les signaux d'horloge CLK1 et CLK2 sont bas, les transistors 222 et 224 pendant une phase de transfert comme cela a été décrit précédemment, et les données deviennent ensuite accessibles sur la sortie D' de la bascule 1000 après le front d'horloge montant suivant du signal d'horloge CLK2.In addition, data may be stored in a nonvolatile manner by programming the resistive states of
Pendant une phase d'écriture des éléments résistifs 202, 204, pour générer un courant à partir du noeud de mémorisation 206, à travers les éléments 202, 204, vers le noeud de mémorisation 210, le signal CLK1 est amené à l'état haut pour activer le transistor 502, et le noeud de mémorisation 206 est couplé à la tension d'alimentation VDD par l'intermédiaire du circuit d'entrée 504.During a write phase of the
Pendant une autre phase d'écriture, pour générer un courant à partir du noeud de mémorisation 210, à travers les éléments 202, 204, vers le noeud de mémorisation 206, le signal CLK1 est par exemple de nouveau amené à l'état haut pour activer le transistor 502, et le noeud de mémorisation 206 est couplé à la masse par l'intermédiaire du circuit d'entrée 504. L'inverseur 1004 va alors appliquer une tension relativement élevée au noeud de mémorisation 210. En outre, le signal d'horloge CLK2 peut être amené à l'état haut pour activer le transistor 902, et le noeud de mémorisation 210 couplé à la tension d'alimentation VDD par l'intermédiaire du transistor 1008, sur la base d'un état bas du signal de données D'.During another write phase, to generate a current from the
Il sera clair pour l'homme de l'art que dans des variantes de réalisation, les positions des registres 1001 et 1002 de la
La
Chaque cellule mémoire 1102 par exemple correspond sensiblement à la cellule mémoire de la
Un bloc de commande de rangées 1104 fournit des signaux de commande sur des lignes de rangées 1105 vers les cellules mémoires, un groupe de lignes de rangées 1105 communes étant prévu pour chaque rangée. Par exemple, chaque groupe de lignes de rangées 1105 comprend un signal de ligne de mot WL pour contrôler les transistors 502, 902 de chaque cellule mémoire 1102. En outre, ce groupe de lignes de rangées 1105 comprend par exemple le signal AZ pour contrôler le transistor 220 de chaque cellule mémoire. Le bloc de commande de rangées 1104 fournit aussi par exemple le signal de transfert TR à chaque cellule mémoire sur une ligne de rangées 1106 correspondante, une ligne de rangées commune 1106 étant prévue pour les cellules mémoires de chaque rangée. Les signaux de transfert contrôlent les transistors 222, 224 de la cellule mémoire 200.A
Un bloc de commande de colonnes 1108 par exemple reçoit des données DV à mémoriser de façon volatile par une rangée de cellules mémoires pendant une opération d'écriture standard, et des données DNV à mémoriser de façon non volatile par chacune des cellules mémoires pendant une phase d'écriture des éléments résistifs 202, 204 de chaque cellule mémoire 1102. Le bloc de commande de colonnes 1108 est couplé à chacune des lignes de bit BL et
En fonctionnement, pendant une phase d'écriture des éléments résistifs 202, 204 dans chacune des cellules mémoires 1102, une seule rangée de cellules mémoires est programmée à la fois. La programmation est par exemple réalisée en activant le signal de lignes de mots WL et le signal AZ de chacune des cellules mémoires de la rangée à programmer, pour activer les transistors correspondant 220, 502 et 902. Cela crée un chemin de conduction entre les lignes de bit BL et
Pour mettre en oeuvre une phase de transfert telle que les données mémorisées par les éléments résistifs 202, 204 soient transférées vers les noeuds de mémorisation 206, 210, le signal de transfert TR et le signal AZ sont activés comme cela a été décrit en relation avec les
En plus de la mémorisation de données de façon non volatile, des données peuvent être mémorisées de façon volatile dans chaque cellule mémoire de la même façon qu'avec une mémoire RAM.In addition to storing data in a nonvolatile manner, data can be stored volatile in each memory cell in the same way as with RAM.
Les
La
L'élément 1200 comprend des électrodes inférieure et supérieure 1202 et 1204, chacune ayant sensiblement une forme de disque, et prenant en sandwich un certain nombre de couches intermédiaires entre elles. Les couches intermédiaires comprennent, du bas vers le haut, une couche fixe 1206, une barrière d'oxydation 1208, et une couche de mémorisation 1210.
La barrière d'oxydation 1208 est par exemple en MgO ou en AlxOy. La couche fixe 1206 et la couche de mémorisation 1210 sont par exemple en matériau ferromagnétique, comme du CoFe. La direction de spin dans la couche fixe 1206 est fixe, comme cela est représenté par une flèche allant de la gauche vers la droite en
La
L'élément 1220 est sensiblement cylindrique, et a par exemple une section qui est circulaire. L'élément 1220 comprend des électrodes inférieure et supérieure 1222 et 1224, chacune ayant sensiblement une forme de disque et prenant en sandwich un certain nombre de couches intermédiaires. Les couches intermédiaires comprennent, du bas vers le haut, une couche fixe 1226, une barrière d'oxydation 1228, et une couche de mémorisation 1230. Ces couches sont similaires aux couches correspondantes 1206, 1208 et 1210 de l'élément 1200, excepté que la couche fixe 1226 et la couche de mémorisation 1230 ont une anisotropie perpendiculaire au plan, comme cela est représenté par les flèches verticales dans les couches 1226 et 1230 de la
Si l'élément STT 1200 ou 1220 de la
Avec la description ainsi faite de plusieurs modes de réalisation illustratifs, diverses altérations, modifications et améliorations apparaîtront facilement à l'homme de l'art.With the description thus made of several illustrative embodiments, various alterations, modifications and improvements will be readily apparent to those skilled in the art.
Par exemple, il sera clair pour l'homme de l'art que la tension d'alimentation VDD dans les divers modes de réalisation pourrait avoir un niveau quelconque, par exemple entre 1 et 3 V, et plutôt que d'être à 0 V, la tension de masse peut aussi être considérée comme étant une tension d'alimentation qui pourrait être à un niveau quelconque, comme un niveau négatif.For example, it will be clear to those skilled in the art that the supply voltage V DD in the various embodiments could have any level, for example between 1 and 3 V, and rather than being 0 V, the ground voltage can also be considered as a supply voltage that could be at any level, such as a negative level.
En outre, il sera clair pour l'homme de l'art que, dans tous les modes de réalisation décrits ici, tous les transistors NMOS pourraient être remplacés par des transistors PMOS, et/ou tous les transistors PMOS pourraient être remplacés par des transistors NMOS. L'homme de l'art saura comment tous les circuits peuvent être mis en oeuvre en utilisant uniquement des transistors PMOS ou uniquement des transistors NMOS. En outre, bien qu'on ait décrit ici des transistors basés sur la technologie MOS, dans des variantes de réalisation on pourrait utiliser d'autres technologies de transistors, comme la technologie bipolaire.In addition, it will be clear to those skilled in the art that in all the embodiments described herein, all NMOS transistors could be replaced by PMOS transistors, and / or all PMOS transistors could be replaced by transistors. NMOS. Those skilled in the art will know how all circuits can be implemented using only PMOS transistors or only NMOS transistors. In addition, although transistors based on MOS technology have been described here, in alternative embodiments other transistor technologies, such as bipolar technology, could be used.
Claims (15)
- A memory cell comprising:first and second resistive elements (202, 204), at least one of which is programmable to have one of at least two resistive states (Rmin, Rmax), a data value being represented by the relative resistances of the first and second resistive elements, the first resistive element (202) being coupled between a first storage node (206) and a first intermediate node (208), the second resistive element (204) being coupled between a second storage node (210) and a second intermediate node (212);a first transistor (214) coupled between said first storage node and a first supply voltage (GND, VDD);a second transistor (216) coupled between said second storage node and said first supply voltage, wherein a control node of said first transistor is coupled to said second storage node and a control node of said second transistor is coupled to said first storage node;a third transistor (220) coupled between the first and second intermediate nodes; characterized bya fourth transistor (502) coupled by its main current nodes between said first storage node (206, 210) and a data input node (506, 906); andcontrol circuitry (534, 934) configured, during a write phase, to activate said third and fourth transistors and to couple said data input node to a second supply voltage (VDD, GND) via a first circuit block (508, 908) to generate a programming current in a first direction through said first and second resistive elements to program the resistive state of at least one of said elements.
- The memory cell of claim 1, wherein said first circuit block (508, 908) comprises at least one transistor coupled between said data input node and said second supply voltage and controlled by input data (D, D') of said memory cell.
- The memory cell of claim 1 or 2, further comprising a second circuit block (510, 910) comprising at least one transistor coupled between said data input node and said first supply voltage and controlled by said input data (D, D') of said memory cell.
- The memory cell of claim 3, wherein said first and second circuit blocks are configured to apply to said input data at least one of the group of logic functions comprising: a multiplexing function; a NOT function; a NOR function; a NAND function; an XNOR function; an OR function; an AND function; and an XOR function.
- The memory cell of any of claims 1 to 4, further comprising a fifth transistor (226, 230) coupled between said second storage node (206, 210) and said second supply voltage (VDD, GND), wherein said control circuitry is further configured, during a further write phase, to activate said third and fifth transistors to generate a programming current in a second direction through said first and second resistive elements to program the resistive state of at least one said elements.
- The memory cell of any of claims 1 to 4, further comprising a sixth transistor (902) coupled between said second storage node (206, 210) and a further data input node (506, 906), wherein said control circuitry (534, 934) is further configured, during a further write phase, to activate said third and sixth transistors and to couple said further data input node to said second supply voltage (VDD, GND) via a further circuit block (508, 908) to generate a programming current in a second direction through said first and second resistive elements to program the resistive state of at least one of said elements.
- The memory cell of claim 3 or 4, further comprising an inverter (1004) coupled between said first storage node and said second storage node, wherein said control circuitry (534, 934) is further configured, during a further write phase, to activate said third and fourth transistors and to couple said data input node to said first supply voltage (VDD, GND) via said second circuit block (508, 908) to generate a programming current in a second direction through said first and second resistive elements to program the resistive state of at least one of said elements.
- The memory cell of any of claims 1 to 7, wherein each of said first and second transistors (214, 216) is connected to said first supply voltage.
- The memory cell of any of claims 1 to 8, wherein at least one of said first and second resistive elements is one of:a spin transfer torque element with in-plane anisotropy;a spin transfer torque element with perpendicular-to-plane anisotropy;a reduction oxide (RedOx) element;a ferro-electric element; anda phase change element.
- The memory cell of any of claims 1 to 9, wherein each of said first and second transistors comprises a bulk node, and wherein said control circuitry is further configured to couple the bulk node of at least one of said first and second transistors to a third supply voltage different from said first supply voltage while said data input node is coupled to said second supply voltage (VDD, GND).
- The memory cell of any of claims 1 to 10, further comprising:a seventh transistor (222) coupled between said first intermediate node and said second supply voltage; andan eighth transistor (224) coupled between said second intermediate node and said second supply voltage.
- The memory cell of claim 11, wherein said seventh and eighth transistors are adapted to have a lower threshold voltage than said first and second transistors.
- A memory device comprising:
an array of the memory cells, each memory cell comprising the memory cell of any of claims 1 to 12, wherein said data input nodes of said memory cells are coupled to first bit lines (BL) of said memory device. - A synchronous memory device comprising:the memory cell of any of claims 1 to 12; anda further memory cell coupled in series with said memory cell, the further memory cell comprising a pair of crosscoupled inverters.
- A method of non-volatile storage of a data value in a memory cell, the memory cell comprising: first and second resistive elements (202, 204), at least one of which is programmable to have one of at least two resistive states (Rmin, Rmax), a data value being represented by the relative resistances of the first and second resistive elements, the first resistive element (202) being coupled between a first storage node (206) and a first intermediate node (208), the second resistive element (204) being coupled between a second storage node (210) and a second intermediate node (212); a first transistor (214) coupled between said first storage node and a first supply voltage (GND, VDD); a second transistor (216) coupled between said second storage node and said first supply voltage, wherein a control node of said first transistor is coupled to said second storage node and a control node of said second transistor is coupled to said first storage node; a third transistor (220) coupled between the first and second intermediate nodes; characterized by
a fourth transistor (502) coupled by its main current nodes between said first storage node (206, 210) and a data input node (506, 906), the method comprising:activating said third and fourth transistors;coupling said data input node to a second supply voltage (VDD, GND) via a first input circuit block (508, 908) while said third and fourth transistors are activated to generate a programming current in a first direction through said first and second resistive elements to program the resistive state of at least one of said elements.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR1353398A FR3004576B1 (en) | 2013-04-15 | 2013-04-15 | MEMORY CELL WITH NON-VOLATILE DATA STORAGE |
PCT/FR2014/050913 WO2014170594A1 (en) | 2013-04-15 | 2014-04-15 | Memory cell with non-volatile data storage |
Publications (2)
Publication Number | Publication Date |
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EP2987168A1 EP2987168A1 (en) | 2016-02-24 |
EP2987168B1 true EP2987168B1 (en) | 2019-03-13 |
Family
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Country | Link |
---|---|
US (1) | US9653163B2 (en) |
EP (1) | EP2987168B1 (en) |
FR (1) | FR3004576B1 (en) |
WO (1) | WO2014170594A1 (en) |
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2014
- 2014-04-15 EP EP14722276.4A patent/EP2987168B1/en not_active Not-in-force
- 2014-04-15 US US14/784,871 patent/US9653163B2/en active Active
- 2014-04-15 WO PCT/FR2014/050913 patent/WO2014170594A1/en active Application Filing
Non-Patent Citations (1)
Title |
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None * |
Also Published As
Publication number | Publication date |
---|---|
US20160064077A1 (en) | 2016-03-03 |
EP2987168A1 (en) | 2016-02-24 |
WO2014170594A1 (en) | 2014-10-23 |
FR3004576B1 (en) | 2019-11-29 |
FR3004576A1 (en) | 2014-10-17 |
US9653163B2 (en) | 2017-05-16 |
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