FR2948482A1 - REMOTE CONTROL DISPLAY DEVICE - Google Patents

Abstract

The invention relates to a remote-controlled image display device comprising at least one display module (MDL) including display cells (CELL) respectively controlled by electronic microcircuits (MCI) in response to data. command received by the display module (MDL). According to the invention, the display module (MDL) comprises means (MCO) designed to transmit the control data to the plurality of microcircuits (MCI) in the form of a serial stream, each microcircuit (MCI) comprising a register shifter adapted to receive the control data stream, and the display microcircuit shift (MCL) registers (MCL) being serially connected to each other.

Description

The invention relates generally to the field of electronic displays, such as for example large format billboards used outdoors.

More specifically, the invention relates to a remote display or video display device, comprising at least one display module including a plurality of display cells and a plurality of electronic control microcircuits each of which is designed. to control at least one display cell associated therewith, each microcircuit controlling each associated cell in response to the detection, by this microcircuit, of control data for said associated cell and belonging to a set of control data received by the display module. A display device of this type is particularly mentioned in the patent application WO 2004/034362. Electronic display devices, examples of which are given in patent documents US 5,309,174, US 2002/0165776, and US Pat. No. 7,369,058, present on traditional billboards, such as billboards using posters. of paper, the double advantage of allowing the display of a dynamic image, and to be able to be updated remotely, that is to say without human intervention on the spot. However, the complexity of an electronic display device grows rapidly with its size, so that the realization of large format billboards, for example 4 meters by 3 meters, is particularly difficult. In this context, the present invention is intended to provide an electronic display device 2 with a structure to greatly reduce the complexity. For this purpose, the display device of the invention, which moreover conforms to the generic definition given in the preamble above, is essentially characterized in that the display module comprises means designed to transmit to the plurality of microcircuits the control data set as a serial stream of control data, in that each microcircuit comprises a shift register adapted to receive the serial stream of control data, and in that the registers Offset of the microcircuits of said display module are serially connected to each other to form a super shift register selectively traversed by the serial stream of control data relating to said display module. In the preferred embodiment of the invention, each microcircuit comprises dedicated memory means designed to store the control data contained in the series of control data and relating to each cell associated with this microcircuit. With this arrangement, the microcircuit has the entire duration of the frame of an image to optimally control each display cell associated with it independently of the properties of the scan such as the resolution of the screen. The centralized management of the displays, especially in terms of downloading, number of images, duration of each image and frequency of image renewal, can then be ensured with great flexibility. In addition, each microcircuit very advantageously comprises operating monitoring means delivering self-diagnosis data. This feature makes it possible to increase the remote management capabilities of the display device by optimizing its maintenance. In this case, the shift register of each microcircuit of the module is preferably designed to selectively enable data flow in any one of two different directions, and this shift register is selectively controlled to output a serial data stream. self-diagnosis in the opposite direction of the serial flow of control data. The display device of the invention can then be controlled from a management center for downloading the advertising screens and to check the correct loading, and to control in real time the correct operation of the device, in particular the level of quality of the screen (number of defective pixels, brightness, drift over time, etc.), which makes it possible to greatly reduce management costs and on-site interventions for maintenance. It is also wise to provide that each microcircuit comprises electrical servocontrol means of each cell associated with this microcircuit and / or optical servocontrol means of each cell associated with this microcircuit. The control characteristics of the display cells, such as the amplitude or duration of the pulses, can then be optimized to obtain the best optical appearance of the pixels of the image and a maximum lifetime of these display cells. The display device of the invention offers the greatest operating flexibility in the case where a single display cell is associated with each microcircuit.

Each display cell comprises, for example, at least one field emission component provided with a cathode, the operation monitoring means can then comprise at least measuring means designed to measure the cathode current of this emission-emitting component. field. The field emission component is for example constituted by a source of luminescent cathode carbon nanotubes used in triode or diode, as known to those skilled in the art by the acronym "FEN" and described in US Pat. 2009-0051261-Al. In the case where each display cell comprises at least one such field emission component, the operation monitoring means may, alternatively or cumulatively, comprise at least measuring means designed to measure the cathode potential of this field emission component. In the case where each display cell comprises at least one field emission component provided with a cathode, the electrical servocontrol means of this cell comprise, for example, means for slaving the cathode current of a fixed value to a fixed value. field emission component. On the other hand, in the case where each display cell comprises at least one luminescent component, each microcircuit advantageously comprises a transistor designed to control a corresponding luminescent component of each associated display cell as a function of representative luminance control data, for each displayed image, with an adjustable duration of activation of this transistor during a predetermined time interval. The optical servocontrol means of each cell associated with a microcircuit may then comprise photometric measuring means designed to compare with a predetermined energy quantum the optical energy emitted by said luminescent component for a fraction of the adjustable duration of time. activation, and switch means for disabling said transistor after the emission of said quantum of energy by the luminescent component. In the case where the device of the invention has significant dimensions, it preferably comprises a plurality of juxtaposed and identical display modules. In this case, it may be advisable to provide that it also comprises a main board with remote transmission means, possibly by satellite, and that this main board is connected to each module by a main data bus system. In particular, it may be desirable to provide that said means designed to transmit a set of control data to the plurality of microcircuits comprise a microcontroller, each module comprises, in addition to the microcontroller, a memory, a memory access controller, two logical gate assemblies, and buses connected to the main data bus system, and that the memory access controller and the logic gate assemblies are designed to selectively provide the main stage or microcontroller with direct access to the memory. Other characteristics and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limiting, with reference to the appended drawings, in which: FIG. 1 is a diagram representing a mode operating a device according to an advanced embodiment of the invention; FIG. 2 is a diagram showing a possible structure of a part of a device according to the invention; FIG. 3 is a diagram illustrating the general architecture, at the central level and at the level of a display module, of a device according to a preferred embodiment of the invention; FIGS. 4 and 5 are flowcharts illustrating possible transactions between a management center and a device according to an advanced embodiment of the invention; FIG. 6 is a diagram illustrating a first exemplary structure of a microcircuit that can be used in a device according to the invention; FIG. 7 is a diagram illustrating a second exemplary structure of a microcircuit that can be used in a device according to the invention; FIG. 8 is a diagram illustrating a third exemplary structure of a microcircuit that can be used in a device according to the invention; and FIG. 9 is a diagram illustrating a fourth exemplary structure of a microcircuit that can be used in a device according to the invention. As previously announced, the present invention relates to a remotely controlled AFF display device IM (FIG. 1). Although the following description refers to several possible embodiments of the invention and describes many features for the purpose of optimal clarification of this invention, it is here explicitly agreed that the necessary character or on the contrary only option 1 of each of the features described below will be determined by the content of the claims. In its most advanced embodiment (FIG. 1), the AFF IM device of the invention can be connected to a CTR management center GST, via a geostationary satellite SAT, via a link L COMM of FIG. sending of operating or display commands, and by a diagnostic L DIAG link. The link L COMM allows the management center CTR GST to address the display device AFF IM commands for changing the operating mode or display of images, while the link L DIAG allows in particular the display device AFF IM to address the CTR GST management center the result of a self-diagnosis, in the form of data relating to the operation of this device AFF IM. As shown in FIG. 2, the AFF IM device comprises one or more MDL display modules, each of which comprises a plurality of electronic control microcircuits MCI, and a plurality of CELL display cells, referenced in FIG. illustrated explicitly. Although each MCI microcircuit may be designed to control a plurality of CELL display cells, each of these microcircuits MCI is preferably designed to control a single CELL display cell associated with that microcircuit. By convention, the word "display cell" here refers to a functional unit for displaying an elementary point or "pixel" of an image. However, since an image may be monochrome or polychrome, each pixel may itself be a monochrome pixel or a color pixel (trichrome). In the case of a monochrome image, the functional assembly intended to display a pixel of this image may for example be constituted by carbon nanotubes with field emission, known to those skilled in the art under the acronym "FEN as described in patent EP 1 15 498 931. On the other hand, in the case of a polychrome image using the same technology, the functional assembly intended to display a color pixel of this image will for example consist of three sources. of carbon nanotubes - FEN. Although a color pixel thus appears to be equivalent to three monochrome pixels, the designation of "subpixels" will be privileged to designate the points displayed by the three carbon nanotube sources 25 FEN which form a functional assembly intended to display a color pixel. FIG. 3 illustrates, inside the dashed frame, one of the display modules MDL and, outside the frame, the components of the device AFF IM 30 which are common to all the modules MDL in case of plurality of such modules. More precisely, the device AFF IM comprises a main board PLAT PRINC and transmission busses 9 of information relating to the system constituted by this device, namely a main control bus SYS CTL BUS, a main data bus SYS DAT BUS, and a main bus of SYS ADR BUS addresses.

The PLAT PRINC main stage includes an image processor, a frame memory and a video interface. These components, well known to those skilled in the art, have not been shown in the figures. The main board PLAT PRINC, which is in connection with the management center CTR GST through the links L COMM and L DIAG, constitutes the electronic circuit of the highest level of hierarchy of the device AFF IM. The electronics of each display module MDL, as shown in FIG. 3, is located at the intermediate level of the hierarchy, and each microcircuit MCI, whose various embodiments are illustrated in FIGS. the lowest of the operating hierarchy of the AFF IM device operation. As shown in FIG. 3, the electronics of each display module MDL comprise, in particular, an MCO microcontroller driving a plurality of microcircuits MCI, an SRAM, two sets of logical three-state ports 3 ST LOG 1 and 3 ST LOG 2 , a DMA CTL controller for direct access memory, a DECOD AD address decoder, control buses, data and address links linked to the MDL module and respectively referenced as MDL CTL BUS, MDL DAT BUS, and MDL ADR BUS, as well as control buses, data and addresses related to the MCO microcontroller and respectively referenced MCO CTL BUS, MCO DAT BUS, and MCO ADR BUS. The DECOD AD address decoder is designed to be able to selectively deliver an Interr interrupt signal to the microcontroller MCO and an authorization signal Autor to the memory controller DMA CTL, this DMA controller CTL being itself designed to selectively deliver control signals Comm to each of the sets of doors 3 ST LOG 1 and 3 ST LOG 2. The control data transmitted by the management center CTR GST on the link L COMM form a control data stream, and each microcircuit MCI comprises an SRG or BIDIR SRG shift register which receives a portion of this control data stream as a serial stream. Moreover, the SRG or BIDIR SRG shift registers of the microcircuits MCI of each display module MDL are connected in series with each other (FIGS. 2 and 3) to form a global shift register, or "super register", which is traversed by the serial stream of control data, or by a serial stream of diagnostic data, relating to this display module. Each microcircuit MCI is identified by an address possibly partially defined by its location in the super register of the MDL module to which it belongs, so that specific control data can be addressed individually to each of the CELL display cells. In the most advanced embodiment and as mentioned above, each microcircuit MCI is further provided with operating control means designed to deliver self-diagnostic data representative of the operation of the cell CELL associated with this microcircuit MCI, the register to BIDIR SRG offset of this microcircuit MCI then being bidirectional. Under these conditions, the super shift register formed by the BIDIR SRG shift registers of the different microcircuits MCI of each display module MDL can be traversed in one direction by the operation control and display data sent by the center. GST CTR management system to the different CELL cells associated with the various microcircuits MCI of this module, and be traversed in the opposite direction by self-diagnostic data emanating from each of these microcircuits and intended for the management center CTR GST. The PLAT PRINC main stage of the AFF IM device receives the video signals emitted by the CTR GST center according to an established protocol. These video signals are stored in the frame memory of this deck, so that the image processor of this platten plane can, after identifying and separating the video data corresponding to the different modules MDL, address these video data to these different modules . Although it is possible in principle to address the video data to the different modules via a serial link, this solution is hardly compatible, in the current state of the art, with the requirements of bit rate and clock frequency. a high resolution display. It is therefore recommended to establish the communication between the image processor of the main PCB PLAT PRINC and the microcontroller MCO of each module MDL by means of the main communication system illustrated, composed of the main buses SYS CTL BUS, SYS DAT BUS, and SYS ADR BUS on which information flows in parallel. Likewise, it is preferable to use a 16-bit rather than an 8-bit data bus to limit the bandwidth of this main communication system. The SRAM memory makes it possible to store the video data relating to the various cells CELL of the display module MDL before sending them to the various microcircuits, as well as the self-diagnosis data emanating from these different microcircuits MCI before they are sent to the main stage PLAT PRINC . This SRAM is accessed using the standard architecture of the MDL CTL BUS, MDL DAT BUS and MDL ADR BUS memory buses of the MDL module. As shown in FIG. 3, the link between the SYS buses CTL BUS, SYS DAT BUS, and SYS ADR BUS of the main system, the buses MDL CTL BUS, MDL DAT BUS, and MDL ADR BUS of the memory of the module MDL, and the CTL BUS MCO BUS, MCO DAT BUS, and MCO ADR BUS of the microcontroller, is performed by the 3 ST LOG 1 and 3 ST LOG 2 sets of logic three-state gates.

More specifically, these two sets of doors make it possible to connect the SYS BUS CTL, SYS DAT BUS, and SYS ADR BUS buses of the main system to the MDL buses CTL BUS, MDL DAT BUS, and MDL ADR BUS of the module memory, while the latter are isolated from the MCO bus CTL BUS, MCO DAT BUS, and MCO ADR BUS of the microcontroller, or to connect the MCO bus CTL BUS, MCO DAT BUS, and MCO ADR BUS from the microcontroller to the MDL buses CTL BUS, MDL DAT BUS, and MDL ADR BUS of the module memory, while the latter remain isolated from the SYS bus CTL BUS, SYS DAT BUS, and SYS ADR BUS of the main system. It is thus possible to access the SRAM memory either from the MCO microcontroller of the MDL module, or 13 from the image processor of the main PCB PLAT MAIN. In the case of a plurality of modules connected to the same buses of the main system, each individual module must be able to detect if a specific command or a packet of video data, sent by the main stage, are actually dedicated thereto. For this purpose, each command or packet of video data, transmitted by the main board, uses the most significant bits of the main bus of SYS ADR BUS addresses to identify the module concerned by this command or these data. The DECOD AD address decoder located at the MDL module precisely serves the purpose of constantly monitoring the most significant bits of the main bus of SYS ADR BUS addresses and responding to the reception of the identification bits of the MDL module by launching the appropriate action in the module. The DMA memory access controller CTL has the function of facilitating and regulating access to the SRAM memory. In fact, the sending of the video data from the main board PLAT PRINC to the MDL module and the storage of this data in the SRAM memory can be done in several ways. The most standard way is to have the PLAT MAIN main board first send the data to the MCO microcontroller, which stores the data in the SRAM. However, this technique complicates the programming of the microcontroller MCO and makes it difficult to combine this task with the reading of the data of the SRAM and with their sending in serial mode to the various microcircuits MCI. A more appropriate solution, which is illustrated in FIG. 3, is to use a DMA memory access controller CTL to enable the main board PLAT PRINC to directly control the SRAM memory of the module MDL without any intervention of the microcontroller MCO. To do this, as indicated above, the 3 ST LOG 1 and 3 ST LOG 1 tri-state gate assemblies are designed to be able to connect the MDL bus CTL BUS, the MDL DAT BUS, and the MDL ADR BUS memory bus from the module to the buses. SYS CTL BUS, SYS DAT BUS, and SYS ADR BUS from the main system while isolating them from the MCO BUS BUS, MCO DAT BUS, and MCO ADR BUS from the microcontroller, which allows the main PCB PLAT PRINC to directly store the data video in the appropriate addresses of the SRAM. To further limit the number of operations to be performed by the image processor of the main PCB PLAT PRINC, this processor can also simply send the video data by the main data bus SYS DAT BUS in "burst" mode, it is that is, without sending the accompanying addresses except for the most significant bits to identify the module concerned, while the DMA CTL controller of the module concerned automatically provides its own addresses using for example a system of auto-increment for the generation of these addresses. FIG. 4 illustrates the organization of operations for loading, in the AFF IM device, an image transmitted by the GST management center CTR. These operations are as follows. 15 41 - The management center CTR GST sends to the device AFF IM a command to load an image; 42 - The device AFF IM is supposed to acknowledge receipt of this command in a given time; a - After three unanswered requests, the CTR GST management center goes into alarm mode and triggers an on-site intervention to verify or repair the AFF IM device; 43 - After reception of the confirmation by the AFF IM device for receiving the image: a - the CTR GST sends image data and information concerning the display; b - the GST CTR sends end of loading information; 44 - AFF IM device is supposed to acknowledge receipt of the end of loading information in a given time; a - After three unanswered requests, the CTR GST management center goes into alarm mode and triggers an on-site intervention to verify or repair the AFF IM device; 45 - After reception of the confirmation by the AFF IM device for receiving the end of loading information, the CTR GST sends the device AFF IM a read command of the displayed image; 46 - The device AFF IM is supposed to acknowledge receipt of the read command in a given time; 16 a - After three unanswered requests, the CTR GST Management Center switches to Alarm Mode and initiates an on-site intervention to verify or repair the AFF IM device; 47 - The device AFF IM sends to the center CTR GST the information relating to the display and information of end of sending; 48 - The CTR GST center analyzes the information relating to the display, switches to alarm mode in the event of an anomaly, and possibly triggers, depending on the anomaly found, an on-site intervention to check or repair the AFF IM device; 49 - In the absence of anomaly, the CTR GST center validates the transaction with the device AFF IM. FIG. 5 illustrates the organization of the operations allowing the verification by the management center CTR GST of the operating state of a device AFF IM. These operations are as follows. 51 - The CTR GST management center sends the AFF IM device a command to verify its operation; 52 - The device AFF IM is supposed to acknowledge receipt of this command within a given time; a - After three unanswered requests, the CTR GST management center goes into alarm mode and triggers an on-site intervention to verify or repair the AFF IM device; 17 53 - After reception of the confirmation by the AFF IM device for receiving the command, the CTR GST sends a request to select a specific test image of the device AFF IM, for example a pattern with 50% of white; 54 - The device AFF IM is supposed to acknowledge receipt of this command within a given time; a - After three unanswered requests, the CTR GST management center goes into alarm mode and triggers an on-site intervention to verify or repair the AFF IM device; The AFF IM device stores the data relating to the display of the test image; 56 - The CTR management center GST sends the AFF IM device a request to send the stored data; 57 - The device AFF IM is supposed to acknowledge receipt of this request within a given time; a - After three unanswered requests, the CTR GST management center goes into alarm mode and triggers an on-site intervention to verify or repair the AFF IM device; 58 - The device AFF IM sends to the center CTR GST the information relating to the display and information of end of sending; 59 - The CTR GST center analyzes the information relating to the display, switches to Alarm mode in the event of an anomaly, and possibly triggers, depending on the anomaly detected, an on-site intervention to check or repair the AFF IM device; 18 60 - In the absence of anomaly, the CTR GST center validates the AFF IM scanning sequence. The previous operations, which are at a higher hierarchy level, involve the execution, at a lower level, of other operations, some examples of which are given below. A first example concerns the sending of a command to an MDL module.

Each action at the level of a module of an AFF IM device is initialized by a command sent by the image processor of the main plate PLAT MA of this device. This processor places the code of the desired command on the main data bus SYS DAT BUS, as well as the identification code of the relevant MDL module on the most significant bits of the main bus of SYS ADR BUS addresses. The DECOD AD address decoder of the MDL module to which the command is intended detects the correct identification code of the concerned MDL module and sends an interrupt command Interr to its microcontroller MCO, which switches to read mode to read the command code via its DAT BUS MCO data bus. The choice of possible commands is very broad and includes in particular the following commands initialization of storage of video data in the SRAM memory; initialization of the sending of the video data to the microcircuits MCI; initializing the self-diagnostic function and storing in the SRAM memory self-diagnosis data relating to the aging or malfunction of a CELL display cell; initialization of the sending of the self-diagnosis data to the main board PLAT PRINC; and initialization 19 in the microcircuits MCI of an optical compensation cycle making it possible to compensate for display anomalies or heterogeneities. To avoid any data conflict on the SYS bus CTL BUS, SYS DAT BUS, and SYS ADR BUS main system, some of these commands are specifically provided for a single module, such as for example the 1 command to send command self-diagnosis data to the main board. For this reason, it is necessary to assign a unique identification code to each of the MDL modules. On the other hand, other commands can be generally used by all the modules at the same time, as is the case, for example, with the command to send video data to the microcircuits MCI. Consequently, the DECOD AD address decoder of each MDL module will have to respond not only to the unique identification code of the module to which it belongs, but also to the common identification code used for all the modules.

A second example of operations performed at each module relates to storing the video data in the SRAM memory of this module. After receiving the corresponding control code and the correct identification code of the module, the main data bus SYS DAT BUS of this module is connected to the corresponding data bus MDL DAT BUS of the memory of the selected module, and isolated from the MCO buses ADR BUS, MCO DAT BUS and MCO CTL BUS of the MCO microcontroller by the 3 ST LOG 1 and 3 ST LOG 2 sets of logical three-state gates, placed for this purpose in an appropriate state. The image processor of the main stage PLAT MA then reads the video data of its frame memory, and sends them burst mode ("burst") via the main data bus 20 SYS DAT BUS, to the SRAM memory of MDL module selected. At the same time, the DMA CTL controller of the selected module automatically generates correct addresses for the SRAM, for example using an auto-incrementing device. A third example of operations carried out at the level of each module concerns the sending of video data to microcircuits MCI of this module. After receiving the corresponding control code and the common identification code used for all the modules, the MCO BUS ADC BUS, MCO DAT BUS, and MCO CTL BUS of the MCO microcontroller of each MDL module are connected to the MDL buses ADR BUS, MDL DAT BUS, and MDL CTL BUS of the memory of this module, and isolated from the bus SYS ADR BUS, SYS DAT BUS, and SYS CTL BUS of the main system by the sets of doors 3 ST LOG 1 and 3 ST LOG 2 placed at this effect in an appropriate state. The microcontroller MCO of each module MDL then reads the video data from the consecutive output addresses of the SRAM memory, and sends this data to the microcircuit chain MCI linked to this module, each microcircuit MCI being part of a very long register shift using a serial communication, for example an asynchronous serial communication protocol. Once all video data has been stored within the SRG or BIDIR SRG registers of the MCI microcircuits, activation of the CELL display cells can begin. A fourth example of operations carried out at the level of each module concerns the collection of self-diagnostic data from the microcircuits MCI of this module. 21 After receiving the corresponding control code and the common identification code used for all the modules, the MCO BUS ADC BUS, MCO DAT BUS, and MCO CTL BUS of the MCO microcontroller of each module are connected to the MDL buses ADR BUS, MDL DAT BUS, and MDL CTL BUS of the memory of this module, and isolated from the bus SYS ADR BUS, SYS DAT BUS, and SYS CTL BUS of the main system by the sets of doors 3 ST LOG 1 and 3 ST LOG 2 placed at this effect in an appropriate state. At the same time, the microcontroller MCO of each module sends a request of self-diagnosis to all the microcircuits MCI of this module MDL, via a serial communication. Each of these microcircuits MCI performs aging measurement of the CELL display cell associated therewith, and / or detects the defect, and returns this self-diagnostic data to the microcontroller MCO. To do this, however, the offset direction of the serial communication must be reversed, which makes it unnecessary to use a bi-directional shift register at each microcircuit MCI, as indicated later. The microcontroller MCO then reads the received self-diagnosis data and stores them at appropriate addresses in the SRAM. A fifth example of operations performed at each MDL module is the sending of the self-diagnosis data to the PLAT PRINC main stage of this module. After receiving the corresponding control code and the correct identification code of the selected module, the main data bus SYS DAT BUS of the AFF IM device is connected to the data bus MDL DAT BUS of the module memory and isolated from the ADR MCO buses. BUS, MCO DAT BUS, and MCO CTL BUS of the MCO microcontroller by 22 sets of 3 ST LOG 1 and 3 ST LOG 2 doors placed for this purpose in an appropriate state. The DMA memory access controller CTL of the selected module automatically generates the correct addresses for the SRAM. The self-diagnostic data is read from the SRAM and sent directly, via the main data bus SYS DAT BUS, to the main PCB PLAT MA, where these data are further processed.

A sixth example of operations performed at each MDL module concerns the launch of an optical compensation cycle of the CELL display cells associated with microcircuits MCI of this module. After receiving the corresponding control code and the common identification code used for all the modules, the MCO microcontroller of each MDL module sends an optical compensation command, via the serial communication, to all microcircuits MCI of this module. These microcircuits then execute, independently of each other, an optical compensation cycle, and store the compensation data in their internal registers, this operation therefore implying no data communication between the microcircuits MCI and the microcontroller MCO.

FIGS. 6 to 9, in which the same references designate the same components, illustrate various possible embodiments of an MCI microcircuit. The microcircuit shown in FIG. 6 is the only illustrated microcircuit that is designed to control only a monochrome CELL display cell, for example formed of a single source of carbon nanotubes with FEN field emission, the microcircuits illustrated at FIG. FIGS. 7 to 9, on the other hand, are designed to control a color CELL display cell, for example formed from three sources of field emission carbon nanotubes FEN 1, FEN 2, and FEN 3, the first of which emits a red color, the second a green color, and the third a blue color. Moreover, only the microcircuit illustrated in FIG. 9 is designed to be able to carry out a self-diagnosis, that is to say capable of delivering self-diagnostic data that can be returned from the AFF IM display device to the management center. CTR GST through the L DIAG link (Figure 1). FIG. 6, which therefore represents the most basic embodiment of an MCI microcircuit, is particularly well suited to controlling a light-emitting cathode FEN source of the type described in patent EP 1 498 931, used in a triode configuration and therefore having an anode, a cathode and a gate.

Although it is a priori possible to control such a FEN component by modulating its gate voltage while keeping its cathode and anode at fixed potentials, it is preferable to control it by controlling the potential of its cathode.

This method makes it possible to control in a very precise manner the light emitted by such a component FEN by controlling the current flowing on its cathode and whose intensity is substantially proportional to the intensity of the light emitted.

In addition, this method makes it possible to operate the cathode current measurement and FEN component control electronics at the floating potential of the cathode, so that the MCI microcircuit only needs to manage the modulation of the potential of the cathode. cathode, which is much lower than the potential difference between the cathode and the gate. This elementary microcircuit MCI could also be used to control the luminous flux emitted by a lamp using the same technology as the FEN component, namely a carbon nanotube emissive cold source and a diode or triode configuration. This system would make it possible to envisage a single production line of lamps independent of the luminous power of the product manufactured. In the illustrated embodiments, the cathode voltage control of each FEN component is realized by a floating high voltage N-type DMOS transistor, referenced DMOS, DMOS 1, DMOS 2 or DMOS 3. When the gate of the DMOS transistor , DMOS 1, DMOS 2 or DMOS 3 is open, the drain potential of this transistor, and therefore the cathode potential of the component FEN, FEN 1, FEN 2 or FEN 3 corresponding, 20 automatically reach a value for which the current cathode component FEN, FEN 1, FEN 2 or FEN 3 is zero. To protect each DMOS transistor, it may be advisable to mount a Zener diode (not shown for readability) in parallel on this transistor so as to trim the drain potential of this transistor to a given maximum value, thereby producing, in the corresponding FEN component, a certain leakage current which can be selected to obtain a predetermined contrast ratio. When the pixel or subpixel consisting of the component FEN, FEN 1, FEN 2, or FEN 3 is activated, the cathode current of this component is measured by the voltage drop across a connected RST resistor. series with the corresponding DMOS transistor, DMOS 1, DMOS 2 or DMOS 3. This cathode current thus measured is compared with an internal reference Voo, and the error signal amplified by a differential amplifier AMP DIFF with high gain is used to adjust the gate voltage of the transistor DMOS, DMOS 1, DMOS 2 or DMOS 3 By using this type of negative feedback control loop, the drain potential of the DMOS transistor is automatically adjusted in such a way that it gives a predefined and very stable value of the cathode current. When the electrical characteristics of the FEN component change, for example due to the effects of its aging, the electrical servo loop formed by the resistor RST, the differential amplifier AMP DIFF, and the reference voltage source Voo causes the potential of cathode to the zero potential by increasing the voltage between the cathode and the gate, to compensate for the decrease in light emitted by the FEN component. As explained above, all microcircuits MCI of the same module MDL are connected in series. More precisely, the SRG or BIDIR SRG shift register of each of the microcircuits MCI of the same module MDL forms part of a super data register which passes through all the microcircuits MCI of this module, the shift registers SRG and BIDIR SRG are simply connected to each other via buffer amplifiers such as AMP TAMP (Figures 6 to 8) or AMP TAMP 1 and AMP TAMP 2 (Figure 9). The data sent by the main board PLAT PRINC to microcircuits MCI of each module MDL via 26 the microcontroller MCO of this module, and which circulate, for example according to an asynchronous serial communication protocol, from one microcircuit MCI to the next from the microcontroller MCO to the last microcircuit of the module, include in particular luminance data of each pixel or sub-pixel. As soon as these luminance data relating to an image frame are loaded into the set of shift registers belonging to the different microcircuits MCI of the same module MDL and which together form the super shift register of this module, the pixel or the subpixels controlled by each microcircuit of this module are activated. Several luminance control techniques, that is to say the gray level, can be used a priori, and in particular the amplitude modulation of the pulses, known by the acronym PAM, the modulation in duration of the pulses, known as PWM, or even a combination of both.

The illustrated embodiments use a modulation of the illumination time fraction of each pixel or sub-pixel, which provides excellent linearity of the luminance scale and allows the use of relatively simple circuits.

To do this, the time is divided into successive time intervals of the same duration, and each FEN component is activated to shine with its nominal luminous intensity during an adjustable fraction of each of these successive time intervals.

For example, for a monochrome image whose luminance has a resolution of 8 bits, each time interval corresponds to the production time of 256 clock pulses, and each pixel can, during each time interval, be activated during a period of time. fraction of this time interval between zero and 255/256, the situation being the same for each sub-pixel of a color image.

The quantity of optical energy emitted by a pixel or a sub-pixel during the period separating two successive clock pulses thus defines an elementary unit of optical energy corresponding to the least significant bit (denoted by 1 LSB) of the luminance code. on 8 bits.

Although the clock signal can be generated by each microcircuit MCI, this clock signal is provided, in all the illustrated embodiments, by a synchronization circuit HLG 0 which extracts this clock signal from the synchronization pulses which are contained in the flow of data flowing in the super shift register of the MDL module concerned, which allows a perfect synchronization of the activation of all the pixels of the same module MDL. Each microcircuit MCI also comprises a luminance register, denoted LUM RG or 3 LUM RG, which is connected to the shift register SRG or BIDIR SRG, and in which are stored the luminance data from this shift register and relating to the microcircuit. MCI concerned, as soon as the luminance data for the current image frame and for all the pixels of the relevant MDL module have been delivered. The presence of these luminance registers LUM RG and 3 LUM RG is particularly advantageous since it makes it possible to exploit the luminance data contained in each of these luminance registers while the luminance data relating to the next image frame enter the SRG or BIDIR SRG shift register, so that the total duration of each frame, which is typically 20ms, remains available and usable to control the FEN components. Each microcircuit MCI also comprises a LUM CTL or 3 LUM CTL counter in which are transferred, at the launch of each new image frame, the luminance data temporarily stored in the luminance register LUM RG, and whose content is decremented to the rhythm clock pulses delivered by the synchronization circuit HLG O.

This counter LUM CTL or 3 LUM CTL also acts, depending on its content, on one or more semiconductor switches, such as SW, and SW 1, SW 2 and SW 3, each of which selectively connects the gate of the transistor DMOS, DMOS 1, DMOS 2 or DMOS 3 to AMP DIFF amplifier. More specifically, the operation of the most basic embodiment illustrated in Figure 6 is as follows. Just before launching a new image frame, the counter LUM CTL receives from the luminance register LUM RG the data, for example coded on 8 bits, which represents the luminance to be given to the component FEN during the duration of the next frame that is, the fraction of this time during which the FEN component must be activated. As soon as this frame is launched, and as long as the content of this counter LUM CTL remains different from zero, the switch SW connects the gate of the transistor DMOS to the amplifier AMP DIFF, so that the component FEN remains activated by the transistor DMOS. As soon as the content of the counter LUM CTL, decremented at the rhythm of the clock signal delivered by the circuit 29 HLG 0, reaches the value zero, the switch SW changes state and opens the gate of the transistor DMOS opens. This operation ensures that the total light energy emitted by the FEN component during a frame is directly proportional to the luminance data contained in the luminance register LUM RG just before the launch of this frame. FIG. 7 illustrates a more elaborate embodiment of a microcircuit MCI, which differs from the embodiment of FIG. 6 in that it is designed to drive a color display cell, for example formed of FEN components. 1, FEN 2, and FEN 3 instead of a monochrome cell. This more elaborate MCI microcircuit could also be used to control the color and luminous flux emitted by a lamp using the same technology as the FEN component, namely a carbon nanotube emissive cold source and a diode or triode configuration.

The embodiment illustrated in FIG. 7, as well as the embodiments of FIGS. 8 and 9, implement a method of sequentially controlling the various components FEN 1, FEN 2 and FEN 3, each of which is therefore controlled, while one-third of the duration of each frame, as is controlled by the FEN component of the embodiment of FIG. 6. In other words, the different elementary colors red, green and blue, of the trichromatic pixel, which are respectively emitted by the components FEN 1, FEN 2 and FEN 3, are activated sequentially. This sequential operation makes it possible to use a single RST resistor and a single differential amplifier AMP AMP to measure and control the cathode current of each of the components FEN 1, FEN 2 and FEN 3. On the other hand, the microcircuit of FIG. following figures comprises three DMOS transistors 1, DMOS 2 and DMOS 3, each of which controls a component FEN 1, FEN 2 and FEN 3 corresponding, and three switches SW 1, SW 2 and SW 3, each of which selectively connects the gate of one transistors to differential amplifier AMP DIFF.

Furthermore, the monochrome LUM RG luminance register of FIG. 6 is replaced by a luminance register 3 LUM RG which is successively loaded by the three luminance data respectively relative to the three sub-pixels to be displayed.

Likewise, the counter LUM CTL of FIG. 6 is replaced by a counter 3 LUM CTL, which is successively loaded by these three luminance data. During the first third of the duration of a frame, the value of the first luminance data is loaded into the counter 3 LUM CTL and decremented at the rhythm of the clock signal supplied by the synchronization circuit HLG 0, the switch SW 1 being controlled accordingly by the counter 3 LUM CTL while the switches SW 2 and SW 3 place the transistors DMOS 2 and DMOS 3 in a state of inactivity. During the second third of the duration of a frame, the value of the second luminance data is loaded into the counter 3 LUM CTL and decremented at the rhythm of the clock signal supplied by the synchronization circuit HLG 0, the switch SW 2 being controlled accordingly by the counter 3 LUM CTL while the switches SW 1 and SW 3 place the transistors DMOS 1 and DMOS 3 in a state of inactivity. Similarly, during the third third of the duration of a frame, the value of the third luminance data is loaded into the counter 3 LUM CTL and decremented at the rhythm of the clock signal supplied by the synchronization circuit HLG 0, the switch SW 3 being controlled accordingly by the counter 3 LUM CTL while the switches SW 1 and SW 2 place the transistors DMOS 1 and DMOS 2 in a state of inactivity. FIG. 8 illustrates a more elaborate embodiment of a microcircuit MCI, which differs from the embodiment of FIG. 7 in that it is provided with an optical servocontrol loop, also present in the mode of Figure 9. In addition to brightness and colorimetric control, this more advanced MCI microcircuit could also control the aging and / or failure of a lamp using the same technology as the FEN component, namely a cold source. emissive type carbon nanotubes and a diode or triode configuration ,. This optical servo loop could also apply to a lamp using a monochromatic source. Indeed, although the electric servo loop using the cathode current measurement of each FEN component provides a stable and accurate control of the light intensity emitted by this FEN component, an optical servo loop using one measurement Direct optical performance of this component FEN can significantly improve the performance of the device. The principle of the control loop used in the embodiments illustrated in FIGS. 8 and 32 is to ensure that the optical energy emitted by each FEN component such as FEN 1, FEN 2 and FEN 3 during the allocated time the least significant bit (1 LSB) of the luminance data, that is to say the time separating two successive pulses of the clock signal delivered by the circuit HLG 0, corresponds exactly to a predefined quantum of optical energy. To do this, each FEN component is designed to be able, at least in the new or fully operational state, to emit this quantum of optical energy for a time less than that which separates two pulses of the clock signal, that is, that is, less than the duration of the LSB of the luminance signal, and each FEN component, at least in the new or fully operational state, is controlled to be illuminated only during the fraction of the duration of each 1 LSB of the luminance signal that is necessary to allow this component to emit the predefined quantum of optical energy.

The optical loop, which makes it possible to compensate for the aging and the performance dispersions of the various components FEN, comprises at least, for each microcircuit MCI, a photo-detector PHOT such as a photodiode or a phototransistor, a source of reference voltage V10r a semiconductor switch SW 0, a capacitor CDS, a comparator CMP, and a logic circuit LOG. Very schematically, the operation of the optical servo loop, for example used to control the operation of the component FEN 1, is as follows. Before any operation of this loop, the capacitor CDS is charged to the reference voltage Vio by the transient closure of the switch SW O. The photodetector PHOT is mounted on the module MDL so as to recover a part of the light emitted by the FEN component 1 to be regulated, and for example arranged to receive the radiation emitted towards the rear of the AFF IM device at the place where the microcircuit MCI is fixed. The current produced by the photodetector PHOT, which is directly proportional to the intensity of light emitted, discharges the capacitor CDS previously charged to the fixed reference voltage V10. The input of the comparator CMP is connected to the terminal common to the photodetector PHOT and the capacitor CDS, so that the output of the comparator CMP changes state when the capacitor CDS is completely discharged. As long as the CDS capacitor is not discharged, the FEN component 1 is activated, at least as long as it has to be in accordance with the value of the luminance signal being read. As soon as the capacitor CDS is completely discharged, the change of state of the output of the comparator CMP can be exploited by the logic circuit LOG to immediately interrupt the activation of the component FEN 1, even before the end of the duration of the 1 LSB of the luminance signal during playback. Thus, the more intense the light emitted by the FEN 1 component, the faster the discharge of the CDS capacitor, and the earlier the deactivation of this component. With this type of time modulation, the amount of energy emitted by the FEN component 1 during the duration of each LSB of the luminance signal is fixed and independent of the efficiency of this component or the effects of its aging. In fact, the embodiments illustrated in FIGS. 8 and 9 do not allow the output signal of the comparator CMP to be used directly to control the moment of deactivation of the components FEN 1 to FEN 3. Indeed, like the photodetector PHOT recover not only the light emitted in turn by the FEN 1 to FEN 3 components but also the ambient light, it is not desirable for the optical compensation to use a value of light intensity acquired in real time, which would lead to a high risk of incorrect control of the luminance of each FEN component. To avoid this undesirable phenomenon, the optical compensation should be applied using a measurement of light intensity acquired in the absence of disturbance by ambient light, for example at night, the result of this measurement being stored for later use at any time.

To this end, the microcircuits illustrated in FIGS. 8 and 9 comprise a DCOD decoder, a PWM counter-register 3, and a high frequency clock HLG 1 whose frequency is for example at least 8 or 16 times greater than that of the signal. The function of the decoder DCOD is to produce a update signal update in response to the detection of a code inserted into the data stream passing through the super-shift register of each MDL module and requiring the update of the quantum value of optical energy. Indeed, as this update is performed only on demand and for example once a night, the microcircuit MCI must be informed of the need to perform this update. Thus, when the code assigned to this operation is detected by the decoder DCOD, the latter triggers an update cycle of the optical energy quantum.

The counter-register PWM 3 has the function of counting and storing, in the form of a number of pulses of the HLG clock 1 at high frequency, the duration of emission of the quantum of optical energy for each of the components. FEN 1, FEN 2, and FEN 3, the counter-register 3 PWM must therefore store three values. Indeed, since the optical efficiency of each of the components FEN 1, FEN 2, and FEN 3 is not necessarily the same as that of the other two components, the duration of emission of the quantum of optical energy must be memorized. for each of these components. At the start of a cycle of update of the quantum of optical energy by the decoder DCOD, the counter-register 3 PWM receives a resetting reset signal which erases the values previously stored in this counter-register, and the capacitor CDS is charged to the potential V10 by transient closing of the switch SW O. Then, the component FEN 1 is activated on the occurrence of a pulse of the clock signal from the synchronization circuit HLG O. The light emitted by the component FEN 1 energizes the photodetector PHOT, which discharges the capacitor CDS, while the high frequency clock pulses delivered by the clock HLG 1 since the triggering of the component FEN 1 are counted and stored in the counter-register 3 PWM. When the capacitor CDS is completely discharged, the comparator CMP changes state and sends the counter-register 3 PWM a Stop signal which interrupts the counting of the pulses of the clock HLG 1 and controls the storage of the pulses counted in this counter. register. The number of pulses of the clock HLG 1 stored in the counter-register 3 PWM then represents the exact duration, measured in number of pulses of the clock HLG 1, of the emission by the component FEN 1 of a quantum of optical energy representing 1 LSB of any luminance data subsequently addressed to that component. The capacitor CDS is then again charged to the potential V10 by transient closure of the switch SW 0 and, at the appearance of the next pulse of the clock signal from the synchronization circuit HLG 0, the component FEN 2 is activated. As previously with the FEN component 1, the light emitted by the FEN component 2 excites the photodetector PHOT, which discharges the capacitor CDS, while the high frequency clock pulses delivered by the clock HLG 1 since the triggering of the component FEN 2 are counted and stored in the counter-register 3 PWM.

The previously described process is thus continued sequentially until the counter-register PWM 3 has memorized the exact duration, measured in pulse number of the clock HLG 1, of the emission of a quantum of optical energy. by each of the components FEN 1, FEN 2 and FEN 3. The information contained in the counter-register 3 PWM can then be used until their subsequent update to provide optical compensation of the components FEN 1 to FEN 3 To this end, the counter-register PWM 3 receives, at the appearance of each clock pulse delivered by the synchronization circuit HLG 0, a recharge signal Rech which has the effect of recharging, in the internal counter of this counter-register 3 PWM, the number of clock pulses HLG 1 stored in the first internal register of the counter-register PWM 3 and representative of the duration of emission of a quantum of optical energy by the component FEN 1. The number loaded in this internal counter is then decremented at the frequency of the fast clock HLG 1 by the pulses from this clock.

When the number loaded in the internal counter reaches zero, the counter-register 3 PWM delivers a signal to the logic circuit LOG which has the effect of causing the deactivation of the component FEN 1 by this logic circuit LOG.

At the beginning of the second third of the frame period, the number of clock pulses HLG 1 stored in the second internal register of the counter-register PWM 3 and representative of the duration of emission of a quantum of optical energy by the component FEN 2 is loaded into the internal counter of this counter-register 3 PWM. The new number loaded in this internal counter is then decremented at the frequency of the fast clock HLG 1 by the pulses from this clock, and the previously described process continues sequentially for the components FEN 2 and FEN 3 as for the component FEN 1. The method previously described implicitly assumes that the photo-detectors PHOT of the different microcircuits MCI have exactly the same operating characteristics, and that the optical coupling between the photodetector and each of the components FEN 1, FEN 2 and FEN 3 is the same for all photodetectors and for all FEN components. Since this assumption may not be spontaneously verified, it is a good idea to carry out a factory calibration cycle to correct any discrepancies. The correction of any deviations may for example be obtained by using, in each microcircuit MCI, a non-volatile register and a digital-analog converter (not shown in the drawings), the converter having the function of delivering, as a reference voltage. V10 of the control loop and for each FEN component, a voltage defined by a value stored in the register and obtained by factory calibration using an external and unique voltage reference, used for all microcircuits MCI.

FIG. 9 illustrates an even more elaborate embodiment of an MCI microcircuit, which differs from the embodiments of FIGS. 6 to 8 in that it is equipped with self-diagnosis means and a bidirectional shift register BIDIR SRG, combined with two amplifiers AMP TAMP 1 and AMP TAMP 2. This microcircuit MCI even more elaborate could also be used to inform a centralized management of a problem of loss of luminous flux or a defect of a lamp using the same technology as the FEN component, namely a carbon nanotube emissive cold source and a diode or triode configuration. The self-diagnosis function in fact implies that each microcircuit MCI is able to send back to the CTR management center GST information concerning the aging, the degradation, and possibly the defectiveness of the pixel or the sub-pixels controlled by this microcircuit, so that the management center can decide the action to be taken in the event of an anomaly, for example the replacement of an MDL display module. The degradation of a FEN component can be detected and evaluated by measuring the drain potential of the DMOS transistor that drives the cathode of that component. As previously explained, the electric servo loop using the voltage reference Voo and the differential amplifier AMP DIFF makes it possible to control the cathode current of each FEN component at a constant value independent of the efficiency of this component. However, in case of degradation of a FEN component, the DMOS transistor associated with this component will have to control the cathode voltage by increasing the potential difference between the cathode and the gate in order to maintain a constant cathode current. Consequently, the measurement of the drain potential of the DMOS transistor is a very good indicator of the degree of degradation of the FEN component: a significant decrease in the drain potential of the DMOS transistor when the FEN component is activated indicates that a significant degradation of this component happened. Insofar as the drain of the DMOS transistor is a high voltage node, the measurement of the drain potential of this transistor is for example carried out by means of a resistive divider bridge such as P 1, P 2, and P 3. Naturally , the phenomenon may be more serious. At some point, degradation of the FEN component can reach a level such that the drain potential of the DMOS transistor should be below the zero potential to maintain a constant cathode current. Since this condition can not be realized, the servo loop can no longer function properly, and the cathode current of the FEN component drops. Although this phenomenon may be partially compensated by the optical servocontrol loop, the aggravation of the degradation of the FEN component may be such that this component can no longer emit the predefined quantum of optical energy during the time allocated for its activation during each LSB of the luminance data. The prevention of this situation can be ensured by verifying that the current flowing through the cathode of each FEN component is greater than zero, and thus that the voltage drop across the measuring resistor RST exceeds a predetermined lower limit. When this voltage drop becomes less than this limit, the replacement of the FEN component or the MDL module concerned is essential. The monitoring of the voltage drop in the RST resistor also makes it possible to detect a situation of sudden destruction or inactivity of a FEN component, resulting for example from a bad contact or the rupture of its bulb. In conclusion, the degradation and possible destruction of one or more of the FEN 1, FEN 2 or FEN 3 components can be effectively detected by measuring the drain potential of the DMOS transistor and the voltage drop across the measurement resistor. RST. In place of the DCOD decoder used in the microcircuit MCI of FIG. 8, the microcircuit MCI of FIG. 9 uses a more advanced DCOD decoder 2 capable of detecting, in the data stream traversing the super-shift register of the module MDL. , not only the code requiring the update of the optical compensation and on receipt of which this decoder delivers a SHIFT signal, but also a code requiring the sending of self-diagnosis data. In response to the detection of the code requiring the sending of these self-diagnosis data, the decoder DCOD 2 delivers a signal Diag which reverses the flow direction of the data flowing in the register BIDIR SRG and which causes the preparation and sending to the microcontroller MCO self-diagnostic data relating to microcircuit MCI.

Inverting the direction of data flow in the BIDIR SRG register involves the activation of one of the buffer amplifiers AMP TAMP 1 and AMP TAMP 2 and the deactivation of the other buffer amplifier, i.e. its passage in a state of high impedance.

The development of the self-diagnosis data is performed by means of an analog multiplexer MUX, a CAN-to-digital converter, and an intermediate register DIAG RG. The function of the multiplexer MUX is to send sequentially to the converter CAN the analog voltage signals representing the operating state of the microcircuit MCI, that is to say the voltage across the measuring resistor RST and the potentials of drain of the different transistors DMOS 1, DMOS 2 and DMSO 3. These signals, converted into digital self-diagnosis data by the converter CAN, are temporarily stored in the register DIAG RG before 42 to be injected into the register BIDIR SRG at final destination from the CTR GST management center, via the MCO microcontroller of the MDL module concerned and via the main PCB PLAT PRINC of the AFF IM device.

Once at the CTR GST Management Center, the self-diagnostic data is analyzed for anomalies and corrective action if necessary. As all the microcircuits MCI of the same module MDL are part of the super shift register of the module, the self-diagnosis data are sent by the various microcircuits, following each other, in the same overall operation. Since the self-diagnosis function is completely independent of the optical servo loop, it can be applied to an MCI microcircuit controlling a single-component FEN monochrome CELL display cell, or to a color display cell using three FEN components. .

Consequently, the self-diagnostic description given above for a color cell MCI microcircuit and provided with an optical servocontrol loop also applies to a monochrome or color cell microcircuit, without a loop. optical servoing.

Claims (15)

CLAIMS. A remote-controlled image display device comprising at least one display module (MDL) including a plurality of display cells (CELL) and a plurality of control electronic microcircuits (MCI) each of which is designed for controlling at least one display cell associated therewith, each microcircuit controlling each associated cell (CELL) in response to the detection, by this microcircuit (MCI), of control data intended for said associated cell and belonging to a set control data received by the display module (MDL), characterized in that the display module (MDL) comprises means (MCO) adapted to transmit to the plurality of microcircuits (MCI) the data set of control in the form of a serial stream of control data, in that each microcircuit (MCI) comprises a shift register (SRG, BIDIR SRG) adapted to receive the serial stream of control data, and in that the registers The microstructures (MCI) of said display module (MDL) are connected in series with each other to form a super shift register selectively traversed by the serial data stream of control relating to said module. display (MDL). 2. Display device according to claim 1, characterized in that each microcircuit (MCI) comprises dedicated memory means (LUM RG, 3 LUM RG) designed to store the control data contained in the serial stream of control data. and relating to each cell (CELL) associated with this microcircuit. 44 3. Display device according to any one of the preceding claims, characterized in that each microcircuit (MCI) comprises operating monitoring means (RST, P 1, P 2, P 3) delivering self-diagnosis data. 4. Display device according to claim 3, characterized in that the shift register (BIDIR SRG) of each microcircuit (MCI) of the module (MDL) is designed to selectively allow a data flow in any one of two in a different sense, and in that this shift register (BIDIR SRG) is selectively controlled to output a serial flow of self-diagnostic data in the opposite direction to the serial stream of control data. 5. Display device according to any one of the preceding claims, characterized in that each microcircuit (MCI) comprises electrical servo means (Voo, AMP DI FF, RST) of each cell (CELL) associated with this microcircuit. (MCI). 6. Display device according to any one of the preceding claims, characterized in that each microcircuit (MCI) comprises optical servo means (V10r SW 0, CDS, PHOT, CMP) of each cell (CELL) associated with this microcircuit (MCI). 7. Display device according to any one of the preceding claims, characterized in that a single display cell (CELL) is associated with each microcircuit (MCI). 8. Display device according to any one of the preceding claims combined with claim 3, characterized in that each display cell (CELL) comprises at least one field emission component (FEN, FEN 1) provided with a cathode, and that the operation monitoring means comprise at least measuring means (RST, MUX, CAN) designed to measure the cathode current of this field emission component (FEN, FEN 1). 9. Display device according to any one of the preceding claims combined with claim 3, characterized in that each display cell (CELL) comprises at least one field emission component (FEN, FEN 1) provided with a cathode, and in that the operation monitoring means comprise at least measuring means (P 1 to p 3, MUX, CAN) designed to measure the cathode potential of this field emission component (FEN, FEN 1 ). 10. A display device according to any one of the preceding claims combined with claim 5, characterized in that each display cell (CELL) comprises at least one field emission component (FEN, FEN 1) provided with a cathode, and in that the electrical servo means (Voo, AMP DIFF, RST) of this cell (CELL) comprise means for slaving to a fixed value the cathode current of this field emission component (FEN, FEN 1). 11. Display device according to any one of the preceding claims, characterized in that each display cell (CELL) comprises at least one luminescent component (FEN, FEN 1), and in that each microcircuit (MCI) comprises a transistor (DMOS, DMOS 1 to DMOS 3) arranged to control a corresponding luminescent component (FEN, FEN 1) of each associated display cell (CELL) according to representative luminance control data, for each displayed image, d an adjustable duration of activation of this transistor 46 (DMOS, DMOS 1 to DMOS 3) during a predetermined time interval. 12. Display device according to claims 6 and 11, characterized in that the optical servo means (V10r SW 0, CDS, PHOT, CMP) of each cell (CELL) associated with a microcircuit (MCI) comprise means photometric measurement means (Vio, CDS, PHOT, CMP) adapted to compare the optical energy emitted by said luminescent component (FEN, FEN 1) for a predetermined amount of energy for a fraction of the adjustable activation time, and switching means (LOG, SW 1 to SW 3) for deactivating said transistor (DMOS, DMOS 1 to DMOS 3) after the emission of said quantum of energy by the luminescent component. 13. Display device according to any one of the preceding claims, characterized in that it comprises a plurality of display modules (MDL) juxtaposed and identical. 14. A display device according to claim 13, characterized in that it comprises a main plate (plaat princ) equipped with remote transmission means, possibly by satellite, and in that this main plate (flat princ) is connected to each module (MDL) via a main data bus system (SYS BUS ADR, SYS DAT BUS, SYS CTL BUS). A display device according to claim 14, characterized in that said means (MCO) adapted to transmit a set of control data to the plurality of microcircuits (MCI) comprises a microcontroller (MCO), in that each module ( MDL) comprises, in addition to the microcontroller, a memory (SRAM), a memory access controller (DMA CTL), two sets (3 ST LOG 1 and 3 ST LOG 2) of logic gates, and buses 47 connected to the main system. of data bus (SYS ADR BUS, SYS DAT BUS, SYS CTL BUS), and in that the memory access controller and the logic gate assemblies are designed to offer selectively, to the main board (PLAT MAIN) or to the microcontroller (MCO), direct access to memory (SRAM).