FR2683365A1 - Flat-panel field-emission display device, and circuit for compensating for irregularities, which can be used in such a display device - Google Patents

Abstract

The invention relates to a flat-panel, field-emission display device. In this device comprising two sets of conductors (14, 16), means (30) situated in the region of each intersection for emitting a beam of electrons, a source is provided applying, to the first conductors, a signal formed by a set of voltage steps, a source applying, to the second conductors, a brightness control signal between two reference potentials, and means setting the amplitudes of the signals delivered by the sources. Application especially to cathode-ray tube display devices.

Description

The present invention relates generally

  display cathode ray tube display devices

  flat neau, with matrix addressing, which use cams

  field emission methods, and more particularly a circuit for achieving brightness compensation in such a display device in order to reduce the effects of emission irregularities, which cause variations

of brightness.

  Cathode ray tubes are widely used in computer a lice monitors

  television receivers, etc. to provide video

  optical information chages This wide use can be attributed to the favorable quality of the display,

  that can be obtained with cathode ray tubes, that is to say

  say color, brightness, contrast and resolution

  A main characteristic of a cathode ray tube enabling these qualities to be obtained is the use of a coating formed of a luminescent substance on a

  transparent side However, standard cathode ray tubes

  The disadvantages are that they require significant physical depth, that is to say a large space behind the effective screen, which makes them bulky and bulky. There are a number of applications important, in which this

  depth requirement is harmful For example, the pro-

  Foundry available for many display devices of compact laptops and operational display devices prevents the use of cathode ray tubes. Therefore, great interest has been brought

  attempts to achieve what are called "dis-

  flat panel display positives "or satisfactory" nearly flat panel display devices "for

  which the depth requirement of a ty-

  spike does not exist, while they have characteristics

  comparable or better display characteristics, for example with regard to brightness, resolution, flexibility of display modification,

  energy point of view, etc. While having led to the

  flat panel display devices, which are useful for certain applications, these attempts have not made it possible to produce a display device which

  is comparable to a conventional cathode ray tube.

  An arrangement of a panel display device

  neau plat is described in US patent N 04 857 799 having for title "Matrix-Aclle ssed Flat Panel Display", d 5 delivered on

  August 1989 by Charles A Spindt and others This agency-

  ment comprises a matrix network of means generating

  individually addressable light, cathodolumi-

  nescent, comprising cathodes combined with light means

  cathode ray tube minescents, which react to a

  electronic bombardment by emi S S i o n rune lu-

  visible matter Each cathode is itself formed by a re-

  bucket of emissive cathodes arranged on a support plate

  port, and the luminescent means are provided in the form of a luminescent coating located on a transparent front plate, which is separated by a very small distance,

cathodes.

  The support plate described in the Spindt et al patent includes a large number of bands

  conductive verticals, which are individually addressable

  Each cathode comprises a multiplicity of spaced conical points of electron emission, which protrude externally, from the vertical strips located on the support plate, in the direction of the front plate. A system of electrically conductive grid electrodes is arranged in the vicinity of the points so as to produce and control the emission of electrons The arrangement of

  grid electrodes includes a high number of ho- bands

  individually addressable terraces, which are perpendicular

  to the cathode strips and include openings

  tures that the emitted electrons can pass through The grid electrode terminals are common to a complete row of pixels which extends across the front face of the support structure, and are electrically isolated from all of the bands of cathodes The anode is

  a thin film of an electric transparent material-

  conductive, such as indium tin oxide, which covers the inner surface of the front plate. The matrix array of cathodes can be activated

  by means of addressing the cathodes and the grids available

  placed perpendicularly in a classical system of addresses-

  matrix wise in general The appropriate cathodes of the display device along a selected strip,

  like for example along a column, can be exci-

  tees, while the other cathodes are not Grids of a selected strip perpendicular to the selected cathode strip can also be excited while the others are not, which has the effect

  that the cathodes and the grids of a pixel present at ni-

  calf from the intersection of the horizontal and vertical bands

  selected can be excited simultaneously, and

  are trying to electrons so as to provide the display of the

desired pixel.

  The Spindt et al patent indicates that it is preferable to simultaneously excite a full row of

  pixels rather than exciting individual pixels

  In addition to this system, successive lines are excited so as to provide a display frame, unlike the sequential excitation of individual pixels in a raster scanning mode. This increases the rate

  of use for each panel, providing a light

increased nosity.

  The present invention relates to the control of the brightness at the level of each pixel, which is a function

  of the intensity of the electron beam current that falls

  bent on the luminescent coating of the anode A tech-

  currently used in business devices

  flat panel cathode ray tube plugging with ma-

  software, consists in using a pulse width modulation to control the brightness at the level of each pixel of the display This technique subdivides the line period into a certain number of intervals, the durations of each of these intervals during '' a single period being associated in accordance with a binary progression Par

  Therefore, for a line period comprising four in-

  tervalles having durations equal to one, two, four and eight units of time, it is possible to provide an illumination of each pixel between zero and fifteen units of

  time within a line period The effect of inte-

  gration of the human optical system and the qualities of

  sistance of luminescent substances combine to convert these light times to different values

  in different levels of brightness intensity.

  A cathode ray tube display device with

  flat panel with matrix addressing, which provides excellent

  slow range of brightnesses, is described in the US patent application, serial number 590 870 filed on October 1, 1990 in the name of Peter C Dunham In this display device,

  the brightness control is carried out by means of the

  requires both duty cycle and applied voltage

  applied to the control lines of the conductors which

  cut A periodically stepped waveform with gradually increasing voltage steps is applied sequentially to line conductors

  binary coded video brightness data is applied

  simultaneously at all column conductors The combined voltages present at the intersections of the selected conductors trigger the appearance of a

  succession of electron emissions on luminescent means-

  cents, which lead to a corresponding sequence

lighting intervals.

  According to a method for forming the shape tips

  taper of the electron emission structure, a

  highly collimated skin of vaporized metal, for example molybdenum, strikes a substantially perpendicular strike to a substrate which has a control electrode formed of a metallic film having micron-sized openings over small cavities A second

  beam, for example formed of a vapor of aluminum oxide

  nium, simultaneously strikes the substrate, but at a very low angle During this double deposition process, the

  substrate is rotated about a central axis.

  The net effect is that the openings are gradually blocked

  by the deposition of a composite material (molybdenum and aluminum oxide), while the metal cones (the electrodes forming cathodes) are formed inside the microcavities "arlefa S that of molybdenum vapor The surrounding composite material the cones and closing the openings is removed later by means

  selective chemical corrosion.

  In cathode ray display devices

  flat panel disks of the type described above, it has been found that variations in brightness in the display device must be kept at a lower value

  at 1% so as to obtain an image of acceptable quality

  table Which greatly contributes to providing a light

  uniformity is the physical uniformity of the cathodes which results from the manufacturing process Since the molybdenum cones in the process described above tend to increase towards the source of the vapor

  of molybdenum, the deposition beam must be strongly col-

  therefore, to obtain uni-

  forms on a surface having dimensions sufficient to be useful as a display device, for example dimensions corresponding to eight cm x eight cm or more, molybdenum must be evaporated from a

  considerable distance, typically 90 cm or more.

  Nevertheless, variations in the molybdenum cones, which result from typical manufacturing processes, which are

  often extensions of semiconductor manufacturing-

  are actually unavoidable It turns out that these variations tend to have a spherical shape across

  of the surface of the display device.

  This is why an object of the present invention

  is to provide a perfect flat panel cathode ray tube

  tionné. A further object of the present invention is to provide a cathode ray tube display device

  with flat panel and matrix addressing, comprising a ring

  cooked to compensate for variations in brightness.

  In accordance with the principles underlying the pre-

  invention, we will describe a device intended to be

  used in a flat panel display device

  taking a support structure having a surface area

  taking a first set of conductors substantially pa-

  runners arranged across the surface and a second

  appears to be substantially parallel conductors arranged across the surface The conductors of the first set intersect the conductors of the second set, while

  being electrically isolated The display device comprises

  also carries means present at each level

  intersection of the first and second sets of conductors for emitting an electron beam current in response to a potential difference between the overlapping conductors The device described serves to control the current of the electron beam delivered by the emission means ,

  at each intersection The system includes

  carries means constituting a first source and coupled to the first set of conductors to apply to these

  last a first signal, which consists of a greater

  rality of steps of different tension levels The dis-

  positive further comprises means constituting a se-

  source cond, coupled to the second set of conductors to apply a brightness control signal thereto, which is controlled between a first reference potential and a second reference potential in response to a binary coded video input signal, the difference of voltage between the voltage level steps of the first signal

  applied individually to the first set of conduc-

  the second reference potential of the com- ponent signal

  demand of a luminosity applied to the second set of

  conductors produces an electron beam current de-

  delivered by the emitting means at the intersection of the conductor of the first set of conductors coupled to the means constituting the first source and of the conductor of the second set of conductors coupled to the means constituting the second source, the beam current

  of electrons varying according to the difference of ten-

  Finally, the device comprises means coupled to one of the means constituting the first and second sources for adjusting the amplitude of the signal sent to them, the adjustment being a predetermined quantity specific to

  each conductor of the set of conductors coupled to-

  so-called means constituting the source considered.

  According to a preferred embodiment

  of the present invention, the adjustment means are

  plés to said means constituting the first source, said adjustment means allowing an adjustment of the voltage levels of each step of said set of steps for each conductor of said first set of conductors, and

  allowing adjustment of the bi-coded video input signal

  nary for each conductor of the second set of conduc-

  teurs. According to another embodiment of the present invention, adjustment means are coupled to said means constituting the second source, said adjustment means allowing adjustment of said signal.

  binary coded video input, for each intersection

  tions of said first and second sets of conductors. The aforementioned device is preferably contained in a flat panel display device

  which further comprises a front structure having a

  conde surface adjacent to the surface of the structure

  support comprising means present on the second sur-

  face and sensitive to an electron beam current for

produce luminescence.

  With this arrangement, the lumino-

  of the individual pixels of a flat panel display device with matrix addressing by means of the application of non-uniform voltages to each axis of the

  addressing matrix, which compensates for varia-

  manufacturing conditions that lead to irregularities in

  the brightness of the display device.

  desired brightness levels are corrected by means of appropriate control voltage settings.

  control voltages are applied by digital circuits

  risk and analog based on data stored in memory devices; these settings are either

  fixed for a given panel size or for a process

  above manufacturing, or are unique and associated with

each individual panel.

  Other features and advantages of the pre-

  sente invention will emerge from the description given below

  after reference to the accompanying drawings, on the-

which:

  FIG. 1 represents a drawing, seen from

  partially torn from a panel display

  flat and typical matrix addressing, in which the dis-

  brightness control positive according to this in-

  vention can be installed; Figure 2 shows a sectional drawing

  transverse of a network of elements constituting a device

  tif electron emission, which can be of the type used in the flat panel display device of Figure 1; FIG. 3 illustrates a step occurring during the process of manufacturing transmitters of FIG. 2 and which shows how this process can lead to irregularities at the tips; FIG. 4 represents a block diagram of a first embodiment of a control circuit for

  brightness which includes means to compensate for irre-

  issuer features in accordance with the principles of pre-

invention;

  FIG. 5 represents correction factors

  tion which can be applied to the row and column conductors of the display device of Figure 1;

  FIG. 6 represents a set of chrono-

  grams useful for understanding the operation of the brightness control circuit of Figure 4;

  Figure 7 shows a lo-

  shown, by way of illustration, of a PROM memory used to control the voltages of the line conductors in the embodiment of Figure 4;

  Figure 8 shows a lo-

  shown, by way of illustration, of a PROM memory used to control the brightness data and the column conductors in the embodiment of Figure 4;

  FIG. 9 represents a block diagram of a se-

  second embodiment of a light control circuit

  thinness, which includes means to compensate for

  issuer features in accordance with the principles of pre-

invention;

  FIG. 10 represents a lo-

  As an illustration, a figure of a PROM memory used for controlling the brightness data of the column conductors in the embodiment of FIG. 9; and the figure it represents a block diagram of a

  circuit, shown by way of illustration, used to determine

  ner brightness corrections which are necessary at the level of the individual pixels of the display

Figure 1.

  Referring to Figure 1, there is shown a partially broken away view of a flat panel display device 10, which includes an enlarged view of part of this device The flat panel display device 10 comprises a glass support plate 12 comprising an intersection of columns electrically

  conductive 14, which constitute the electrodes forming

  thodes, and electrically conductive lines 16, which constitute the grid electrodes A glass plate

  front 20, which has a luminescent coating 22 at the ni-

  calf from its inner surface and constitutes the electrode-

  mant anode, extends above this configuration, everything

being spaced apart.

  The part shown on a larger scale in Figure 1 shows a sectional view of an intersection 32 of a row and a column, and shows in more detail the individual elements of the grid electrodes and cathodes of a electron emission device 30,

  taken as an example and present at the level of each in-

  tersection 32 of this type The transmitting device

  of electrons 30 located at the intersection 32

  takes the conductive column 14 and the conductive line 16 separated by an insulating layer 34 In addition, at each intersection 32, there is a plurality of generally circular openings 36 formed in

  column layer 14 and below which are

  it placed cavities 38 formed in the insulating layer 34

  and hollowed out to the level of the layer forming line 16.

  In each cavity 38 is disposed a conical metal structure 40, which is electrically coupled to the layer forming a conductive line 16. This conical structure 40 is the part of the cathode electrode, starting from

  from which the emission of electrons takes place which is

  picked up by the field The tip of each conical structure is located approximately at the upper level of the column layer 14 and is preferably centered in

an opening 36.

  Referring to Figure 2, there is shown a cross-sectional drawing, on a greatly increased scale, of an embodiment of a thin film of cathode and grid electrodes, which may be of the type comprising the device electron emission located

  at the intersections between the lines and the co-

  lonnes in the present invention The electron emission device 30 comprises an electrically insulating substrate 12, glass for example, on which is disposed a

  conductive layer 16, for example a metal such as mo-

  lybdenum, which is used as a common conductor for

  all cathodes 40 A layer 34 of an electro material

  The insulating layer is attached to the conductive layer 16, and a second thin conductive layer 14, which forms the gate electrode, covers the layer 34. A plurality of openings 36 formed in the layer 14 pass through the insulating layer 34 to the conductive layer 16, in

  forming a plurality of cavities 38 in the device 30.

  Cathodes 40, which are located inside each

  of these cavities 38, comprise structures of general shape

  conical mineral made of a conductive material, by

  example a metal such as molybdenum, and which are inter-

  electrically connected through their

  contacts to the conductive layer 16.

  The technical specialist will understand easily-

  how can we make the device 30

  as shown in Figure 2, for example in use

  well known photolithographic processes In re-

  sumé, according to a preferred process, a layer of mo

  lybdenum on the glass substrate 12 and it is corroded

  niere to form the line conductors (cathodes) 16, which typically have a thickness of 0.75 microns is deposited by vacuum evaporation a film of oxide 34, for example silicon dioxide (Si O 2) on a thickness

  about 0.75 micron, on the metallized substrate 12 of ma-

  it serves as a spacer and electrical insulator between the line conductors 16 and the conductors of

columns 14.

  A second layer of molybdenum is deposited on the insulating oxide film 34 and corroded so as to

  form the column conductors (grid) 14, which have

  tooth typically also has a thickness of 0.75 mi-

  cron During this second corrosion operation,

  a network of holes 36, each of which has a diameter approximately equal to one micron, is also created by corrosion in the grid electrode layer 14 and in the insulating oxide layer 34, so that they extend

  up to the electrode layer forming cathode 16 The pro-

  reactive ionic corrosion stops, used in a typical way

  pits to form holes 36 in the oxide layer 34, produces a slight underlying corrosion below the grid electrode layer 14, leaving the edges of the openings 36 slightly overhanging, as shown in

Figure 2.

  The cathodes 40 are all formed simultaneously in the cavities 38, typically by evaporation under vacuum of molybdenum, in a direction perpendicular to the substrate 12 Before and during this evaporation,

  vacuum deposition of materials that can be eliminated chi-

  mically, such as 1 aluminum, with an inci-

* almost grazing dence, while rotating the substrate 12 around an axis extending in the direction of the deposition of molybdenum, which causes a gradual closing of the holes 36 formed in the gate electrode 14, which passes through molybdenum evaporated, so as to form a layer

  stop, whose diameter decreases, which eventually leads-

  also the formation of emitters of co-shaped fields

  pic 40, whose points are located approximately

  in the upper surface of the grid electrodes 14.

  During the final step of manufacturing the electron emission device 30, the material of the aluminum barrier layer is dissolved and removed from the periphery and

  inside the holes 36 and the cavities 38.

  Ideally, the conical shape and the dimensions are almost identical between all the cathodes 40, the

  radius of the tips being equal to about 30-40 nanometers.

  However, the physical limitations of the manufacturing process

  tion, as described above, prevent

  obtaining such uniformity The operating stage il-

  glossy, on an exaggerated scale, in FIG. 3, leads to variations in the shapes and dimensions of the cones 40

  on the extent of the transmitting structure 30.

  Figure 3 illustrates the stage of evaporation of the mo-

  lybdenum, in which the conical cathodes 40 are formed on the emitting structure 30 (To facilitate

  the description, the device used has not been represented

  to effect the simultaneous deposition by evaporation of the material of the barrier layer) A source 50 of evaporated molybdenum directs vapor beams 52 onto a structure 30, of

  typically from a distance of 90-150 cm Because of

  sound of the different angles of incidence of the beams 52 on the front surface of the structure 30, the cones 40 take

  different shapes over the extent of the structure 30.

  Three parts of the structure 30 are shown.

  tees according to enlarged views in Figure 3 a left part, a central part and a right part The left part represents an eccentric cone a, the tip of which is inclined towards the right edge of the opening in the grid electrode 14 a The central part represents a symmetrical cone 40 b, the point of which is generally arranged in a centered manner in the opening of the grid electrode 14 b The right part represents an eccentric cone 40 c, the point of which is inclined towards the left edge of the opening in

the gate electrode 14 c.

  Referring to Figure 4, we see represented

  a device for controlling the brightness of a device

  Display device with flat panel cathode ray tube and matrix addressing of the type shown in FIGS. 1 and 2 and described in the preceding paragraphs The brightness control is carried out by means of the control of both the duty cycle and the voltage applied to conduc-

  control elements for overlapping columns and rows.

  A waveform with voltage steps that increase

  lie gradually is applied to a conductor se-

  lected, along an axis The voltages at each level are preferably selected so as to allow obtaining electron beam currents which provide brightness levels equal to twice the brightness of the previous level Signals of

  binary coded brightness control are applied if-

  simultaneously to all the conductors on the other axis

  mement to the principles of the present invention, the tensions

  of the stepped waveform and the bi-coded signals

  nary include a combination of information data

  video and correction data, which compensate for

  regularity of the emission structure at the level of the conduits

  Selectors The combined voltages at the

  intersections of these selected conductors appear

  a series of electron emissions which

  feels at a corresponding sequence of intervals

  The human optical system integrates this

  quence of illumination which leads to the selected brightness level In addition, the overall brightness of the display device is controlled by means of the transfer of the waveform in the conductor on one or the other axis, by means of '' a pulse train comprising a sequence

  of uniform width adjustable pulses.

  If we consider the device for controlling the

  thinness of Figure 4, which is more detailed, we see

  shown a flat panel display 70

  carrying a multiplicity of column control conductors 72 (1), 72 (2), 72 (256), collectively referred to as the column control conductors 72, and a multiplicity of conductors 74 (1), 74 (2) ,, 74 (256) line control, collectively referred to as 74 line control conductors Intersections

  column control conductors 72 and conduits

  line control elements 74 are located at the level of the field electron emitters 76 (1,1), 76 (1,2),

  76 (1,256), 76 (2,1), 76 (2,2) ,, 76 (2,256),

  76 (256.1), 76 (256.2) ,, 76 (256.256), collectively designated

  vement as being emitters 76 of field electrons.

  For the convenience of the representation as well as to simplify the understanding, it is assumed that in this

  example, the display panel 70 is a display device

  monochrome plug with a 256 x 256 display matrix Consequently, the described embodiment comprises 256 conductors 72 for column control and 256

  Line control conductors 74 Nevertheless, we understand

  will take that the principles indicated here are also ap-

  plicable to color display devices as well as a matrix of any size, including the

  640 x 400 standard VGA system or higher.

  It will also be assumed that the system of representation

  video graphics station (not shown), which sends the

  video control signals to the light control device

  nosity according to the present invention, provides an 8-bit word of brightness data, designated by the term VIDEO DATA, for each pixel of the display device, which makes it possible to have 28 = 256 levels of display brightness

for each pixel position.

  The brightness control device shown

  felt in Figure 4 includes a shift register 80 to

  256 bits, whose output signals are coupled to the circuit

  baked lock 82 The 256 output signals ver-

  rusted are transmitted individually to a first

  door entry terminal ET 84 (1), 84 (2) ,, 84 (256),

  signed collectively under the expression doors ET 84 The doors ET 84 are individually coupled to floors

  attack 86 (1), 86 (2) ,, 86 (256), designated collective-

  ment under the term attack stages 86 In the present example, the attack stages 86 are preferably of the pole-totem type, and are sensitive to input signals at logic level by means of the application of one or more of the other of their two supply voltages at their output terminals In the present example, the supply voltages applied to the drive stages 86 are equal to zero volts and the reference voltages VREF typically equal to approximately 30 volts Each attack stage

  86 (i) commands a corresponding conductor 72 (i) of

  column head of the pan-shaped display

  neau 70 A circuit forming a monostable multivibrator

  glable 88 controls the second input terminal of all

  gates ET 84 by applying a control pulse to the

  adjustable value for each set of data entered in a clocked fashion in locking circuits 82

  durations of the pulses delivered by a multi-circuit

  monostable vibrator 88 are adjusted by means of the

  command designated by "brightness adjustment".

  The line control conductors 74 of the

  positive display in the form of a panel 70 are individually controlled by pole pole stages 90 (1), 90 (2), 90 (256), which will be collectively referred to as attack 90 The attack stages 90 are sensitive to the logic level voltages applied to their input terminals by the counter / decoder 92 for the application of one or other of their supply voltages to the conductor 74 of line control In the present example, the supply voltages coupled to the drive stages 90 are VREF and a voltage waveform VLIGNE In the preferred embodiment, VLIGNE

  includes a stepped waveform with voltages

  sions which generally increase and includes in this example nine voltage levels designated by V 0, Vi,

  V 2 ,, V 8 The values of V O to V 8 are specific to each

  any of the 256 lines shown Successive levels of

  Vi are produced substantially in synchronism with the ver-

  rusting of data coming from the shift register 80, in locking circuits 82 FIG. 5 shows

  a graphic representation illustrating the range of corrections

  tations of lines on the face of a ty-

  spike, which can be fed by memo data words

PROM 116 memory.

  Referring again to Figure 4, the comp-

  teur / décoder 92 is sensitive to a succession of transi-

  tion of voltage at its input terminal by sequential validation of its output terminals In

  the practical implementation of these circuits, the comp-

  teur / décoder 92 and the stages of attack 90 function so that the waveforms of the tension of lines are

  applied individually to an appropriate conduc-

  74 (j) line order tutors, while the conduc-

  Non-severed line order tutors remain at VREF.

  A timing signal, designated as CLOCK in Figure 4, has a frequency which corresponds to nine times the rate at which VIDEO DATA is delivered. The CLOCK signal is applied to an interval counter, which outputs an output signal having a only

  timing control front after each ninth ap-

  CLOCK signal appearance The CLOCK signal is also

  applied to the counter / divider 124 which divides, according to a di-

  binary vision, the signal CLOCK by the number of columns present in the display panel 70, namely 256 in the present example The counter / divider 124 acts additionally as a counter by delivering an output signal having a single edge of order clocked

  after each 256th appearance of the CLOCK signal.

  The output signal delivered by the counter 110

  is transmitted as a clock input signal to the comp-

  column divider / divider 112, which divides, according to a divi-

  binary sion, its cadence input signal by the number of column conductors The counter / divider 112 also acts as a counter by delivering an output signal having a single timing control edge after each 256-th appearance of its input signal from

order clocked.

  The eight binary division outputs delivered by the column counter / divider 112 are sent, in the form of addressing input signals, to the PROM memory 118 and to the addressing inputs in read mode of a RAM memory. with two ports 120 The counting signal delivered by the counter / divider 112 is transmitted as a timing input signal to the line divider 114 and, via a level shift device 96, to the counter / decoder 92 The line divider 114 divides, according to a binary division, its clock input signal by the number of line conductors, 256 in this example The eight output signals of the binary line divider 114 are transmitted as that bits

addressing to the ROM memory 116.

  The eight binary division output signals of the counter / divider 124 are transmitted to the addressing inputs in recording mode of the RAM 120 to two

  ports The count signal delivered by the comp-

  splitter / divider 124 is transmitted as a clock input signal to divider 126, which divides its clock input signal by binary number of brightness control data bits for each pixel in binary division display, new in this example The four output signals from the counter's binary divider

  of intervals / divider 110 are transmitted as if-

  addressing input signals to the PROM memory 116 and as selection input signals to the multiplexer 122 The signal delivered by the counter / divider 124 is also

  transmitted as a trigger signal to -multivi-

  monostable 88 brator The monostable 88 multivibrator de-

  delivers control impulses including ET 84 gates

  the duration is adjustable by the BRIGHTNESS CONTROL signal.

  In the embodiment of FIG. 4, the PROM memory 116 stores 8-bit representations of the

  analog voltage levels for each of the nine inter-

  valleys during a display period, for each of the 256 lines on the display panel 70 For configuration

  given as an illustration of the PROM 116 memory represented

  shown in FIG. 7 and described in the appended text, the

  four output signals from binary divider 126 are input

  seen as the four weight addressing bits

  the weakest ones, to PROM 116 memory, and the eight si-

  output signals from the binary line divider 114 are output to form the eight most significant address bits The eight data output transmission lines, which start from PROM 116, are connected to the digital converter / analog 100, which delivers voltage levels to its output terminal

  corresponding to the eight-bit digital words, which are re-

  received from PROM 116 memory.

  The output signal delivered by the digital / analog converter 100 is transmitted to the adjustable voltage drive stage 102, the output signal of which sends the

  VLIGNE signal to a rail of the line 90 attack stages.

  A similar adjustable voltage driver 104, which is coupled to a voltage source, supplies the voltage VREF

  to rails connected to both the co-

  lonnes 86 and to the line drive stages 90 The voltage control stages 102 and 104 are adjustable so as to allow the correct selection and conservation of the values of VLIGNE and VREF for the delivery of the signals

  desired from the electron beam current.

  The eight output signals from the binary divider of the column counter / divisors 112 are transmitted as addressing input signals to ROM 118 The eight signal lines of a typical eight-bit VIDEO DATA signal are also coupled as addressing inputs to PROM 118 memory For configuration, for example, of PROM 118 memory

  shown in Figure 8 and described in the text an-

  attached, the eight output signals of the binary divider of the counter / divider 112 are sent in the form of the eight most significant addressing bits to the PROM memory 118, and the eight transmission lines of the VIDEO DATA signals are connected way to deliver the eight bits

  addressing the lowest weights.

  In accordance with the principles of this invention

  tion, the PROM memory 118 contains data words vi-

  9-bit deo, which allow individual correction of the 8-bit input VIDEO DATA for each of the 256 columns in the embodiment described Figure 5 shows a graphical representation which illustrates the range of column corrections on the face of a sign

  typical display, which can receive cor-

  rection in the words of 9-bit video data stored in the PROM memory 118 Referring again to FIG. 4, the nine lines of data outputs coming from the PROM memory 118 are connected to the RAM memory 120 to

  two ports, which store 256 words of nine bits each.

  The preferred embodiment of the present invention relates to a system, in which all the pixels of a line are excited simultaneously. In this regard, a requirement is that the shift register 80 is loaded with corresponding bits of all the words. for transmitting brightness data of an entire line, i.e. all the bits O of the 256 pixels of line 74 (j), followed by all bits 1 of the 256 pixels of line 74 (j) , followed by all bits 8 of the 256 pixels of line 74 (j), followed by all bits O of the 256 pixels of line 74 (j + 1), etc. In addition, the RAM 120 stores

  the 9-bit video data word, to which access is reachable

  read from PROM 118, using the address

  simultaneous sage from the column counter / divider 112 Simultaneously, the counter / divider 124 performs a

  cyclic operation passing through its 256 address states

  wise, with sequential reading of 256 words of visible data

  9-bit deo, which corresponds to 256 columns, in a

  9-of-1 multiplexer 122 Divider 126 controls fa-

  sequential lesson the multiple selection input signals

  tiplexer 122, which performs the control of a single binary position from each of the 256 columns, which causes the sending of a single next binary from each of the 256 columns, etc., at the input of the data in

shift register series 80.

  In the previous discussions, the circuit as-

  associated with the 72 column control conductors, that is

  say shift register 80, the latch circuits

  stage 82, the AND gates 84 and the drive stages 86, and the circuit associated with the line control conductors 74, that is to say the counter / decoder 92 and the drive stages 90, have been described with reference to their functions

  However, specialists in the technique of dis-

  video display positives will see that the described functions of each of the column and row circuits in N-bit slices can be included in a single device. Such a device is, by way of illustration, the model system HV 53 / HV 54, marketed

  by Supertex, Inc, of Sunnyvale, California.

  However, it should be noted that when a device

  such as that described in the previous paragraph is used

  read as a line control circuit according to the present invention, in which the reference potential

  (VREF) differs significantly from the referral potential

  rence (O volt) of the rest of the circuit, a circuit 96

  the voltage level is necessary to achieve

  the interface between the two tension systems.

  Referring to Figure 6, we see represented

  an illustrative example comprising a series of plots,

  brought to the time axis and which are useful for understanding

  hension of the operation of the light control circuit

  sity according to the present invention Line (a) illustrates a line period of 50 ps, which is divided into nine equal segments of 5.33 ps each, and a guard band of 2 gs

  nine segments of the line period are designated by seg-

  ment 0, segment 1 ,, segment 8, according to the nine bits of the brightness control data for each

display device pixel.

  Line (b) in Figure 6 illustrates a shape

  voltage wave taken as an example, which is applied

  as one of the line conductors As can be seen, the line conductors are normally placed at a

  VREF voltage; when the line period of the line is

  particular interest is reached, a waveform typically represented by trace (b) is

  applied to the line conductor, and increases

  from a value for V O in a range of values

  their, up to a value for V 8 in a range of values

  their, during the corresponding segments of the line period Each step of the waveform can take a value lying in the range represented between the

  lines formed by dashes of the plot (b), the range represents

  both the extent of correction of the transmitter current required

  to take into account irregularities of the panel

display 70.

  Line (c) in Figure 6 represents the caden-

  cementing of the nine bits of the brightness data, as they

  appear in series in the i-th line of the circuit

  baked lock 82 and are applied as a don-

  born from columns at an input terminal of gate ET 84 (i).

  Line (d) represents the column control signal,

  as it can be produced by a multi- circuit forming

  monostable brator 88 and applied to the other input terminal of the AND gate 84 (i), for the delivery of the overall brightness of the display device and for the reduction of

  transient switching phenomena The trace (e) represents

  feel the timing of the output signal delivered by the

gate AND 84 (i).

  The plots (f), (g) and (h) of figure 6 represented

  feel a particular example of command data from

  brightness which are applied to one of the co-conductors

  lonnes 72 (i) via latch 82, AND gates 84, and column feed stages 86 In this example, the brightness control data has been arbitrarily selected as: 001001101, a abbreviated representation for bit O = 1, bit 1 = 0, bit 2 = 1, bit 3 = 1, bit 4 = 0, bit 5 = 0, bit 6 = 1, bit 7 = O and bit 8 = O This results that the waveform of trace (f) is produced by the column driver 86 in the column conductor 72 (i), the voltage being reduced to 0 volts from VREF only during the commanded periods of the selected bits (bit = 1) Column conductor 72 (i) intersects a selected line conductor 74 (j) which has a voltage waveform

  as shown on the plot (b) of figure 6.

  Since the column conductor 72 (i) understands

  an electrode forming an electron emitter cathode at the

  pixel 76 (i, j) and the line conductor 74 (j) includes the gate electrode of the electron emitter at pixel 76 (i, j), then the waveform of grid-cathode voltage at the selected intersection is

  represented on the plot (g) The voltages V O to V 7 are se-

  selected to provide beam currents

  of electrons associated in accordance with a bi-

  which has been corrected for the line conductor by

  particular 74 (j) which is addressed therefore the current waveform of the beam, which is shown on the

  path (h) in Figure 6, is produced in response to the data

  brightness control results from this example, i.e.

  the individual pulses 20 = 1, 22 _ 4, 23 = 8 and 26 -

64 current units.

  It will be noted, from the waveform of the plot (g), that each time that the segment t of a period of

  line, for which the light control data bit

  nosité is zero, that is to say that we have the bit t = 0, it

  there is a measurable grid-cathode voltage, which is com-

  taken between a minimum value (V O VREF) for the bit O

  and a maximum value equal to (V 8 VREF) for bit 8.

  Nevertheless, the maximum value of the grid-cathode voltage for a bit of brightness control data equal to zero, (V 8 VREF) for time segment 8, is still sufficiently lower than the minimum value of the voltage

  cathode grid for one bit of light control data

  nosity equal to one, V O in time segment 0, so that the beam current emitted thereby is insignificant compared to i O. Referring now to FIG. 7, we see represented there a logical organization, given as

  illustration, from ROM 116 of the embodiment

  sation of Figure 4 As has been described with reference to Figure 4, the PROM 116 is arranged under the

  form of a 4 K x 8 device (4096 words of 8 bits each

  cun), containing 8-bit digital representations of the analog voltages to be applied to the conductors

  individual lines 74 (i) More specifically, the mete

  PROM 116 as shown in Figure 7, contains nine digital words, which represent the voltage levels of the nine intervals of each word of video data, for each of the 256 line conductors 74 due to the convenience of a d addressing, seven words of memory following each set of nine digital representations of analog voltages do not

are not used.

  Technical specialists will also understand

  mean that the nine intervals of each word of video data can be increased to a value of up to sixteen intervals, at no additional cost to PROM 116 memory, simply by using memory locations that are not used in the case of this example given by way of illustration In addition, it will also be understood that it is possible to obtain an order

  more precise line voltages by increasing the word size of the PROM 116 memory beyond the eight bits ac-

* shown as a whole, which also requires a corresponding change in the number of digital input signals to be processed in the digital / analog converter 100. Such an increase makes it possible to de-

  finer settings for brightness correction.

  Referring now to Figure 8, there is shown a logical organization, indicated as

  illustration, PROM memory 118 of the reaction form

  Reading of FIG. 4 As described with reference to FIG. 4, the PROM memory 118 is arranged in the form of a 64 K × 9 device (65,536 words of each 9

  bits), containing 9-bit words used for trans-

  put the brightness data to the individual conductors

  dual columns 72 (i) More particularly, the PROM memory 118 as shown in FIG. 8 contains, for each of the 256 column conductors 72, 256 9-bit digital words which represent the corrected digital values of the 256 corresponding levels of data

8-bit video input.

  In the representation of FIG. 8, for the pixels of column 1, an 8-bit video input data word corresponding to O (in binary: 00000000) corresponds to a 9-bit video data word corresponding to 3 ( in binary: 000000011); an 8-bit video input data word corresponding to 1 (in binary: 00000001) corresponds to a corrected 9-bit video data word corresponding to 5 (in binary: 000000101); one word of video input data

  with 8 bits corresponding to 2 (in binary: 00000010) corres-

  responds to a word of video data corrected to 9 bits corresponding to

  dant to 6 (in binary 000000110); an 8-bit video input data word corresponding to 3 (in binary: 00000011)

  corresponds to a corrected 9-bit video data word

  corresponding to 8 (in binary: 000001000) ,, an 8-bit video data input word corresponding to 254 (in binary: 11111110) corresponds to a corrected 9-bit video data word corresponding to 286 (in binary: 100011110 ); and an 8-bit video input data word corresponding to 255 (in binary: 11111111) corresponds to a 9-bit corrected video data word corresponding to 288

  (in binary: 100100000) Although this is not shown

  felt explicitly, it is felt that the corrections

  for 256 words of 8-bit video input data may

  may be different for each of the 256 column conductors 72. Those skilled in the art will note that there must be another increase in the sensitivity of the corrected numerical value of each video input word, the length of each of the 64 K words in PROM memory 118 should be increased from the nine shown for illustration in this example and that the number of intervals of

  each word of video data must be increased accordingly

  corresponding Such an increase allows more degrees

  precise brightness correction.

  Referring now to Figure 9, there

  sees represented a block diagram of a second form of reaction

  Brightness control circuit which includes

  takes steps to compensate for irregularities

  issuers, in accordance with the principles of this

  vention The embodiment of FIG. 9 differs from that of FIG. 4 in that it allows independent compensation for the brightness of the transmitter for each individual pixel. The cost of this increased capacity is a much more extensive PROM memory, which contains the 9-bit words used to convert the brightness data

  in the individual column conductors 72 (i) The ma-

  part of the structure of the embodiment of Figure 9 is identical to the corresponding elements of the

  embodiment of Figure 4; these elements iden-

  ticks have been designated by the same reference numbers

  rence. A CLOCK signal, which has the same frequency as the corresponding signal of the embodiment of Figure 4, is transmitted to an interval counter 110, which delivers an output signal having a single edge

  command clocked after each ninth appearance of the if-

  general CLOCK The CLOCK signal is also sent to the counter / divider 124, which divides the CLOCK signal, according to a binary division by the number of columns present in the display panel 70, 256 in this example The counter / divider 124 acts in additionally as a counter by delivering an output signal having a single control edge clocked after each 256-th appearance

of the CLOCK signal.

  The eight outputs of the binary divider of the comp-

  tor / divider 124 are coupled to the addressing inputs of

  two port RAM 120 memory read modes If

  the counting signal delivered by the counter / divider 124 is transmitted as a clock input signal to the divider 126, which divides, according to a binary division, its clock input signal by the number of bits of the data of brightness control for each display pixel, new in this example The four output signals of the binary divider of the interval counter / divider 110 are transmitted as addressing input signals to the

  PROM 130 memory and as selection input signals

  tion to the multiplexer 122 The counting signal delivered by the counter / divider 124 is also sent as

  trigger signal to monostable multivibrator 88.

  The monostable multivibrator circuit 88 sends, to the

  gates ET 84, trigger pulses, the duration of which

  The setting is adjustable by means of the BRIGHTNESS CONTROL signal.

  Since the embodiment of the fi-

  gure 9 allows compensation for irregularities

  transmitters for each individual pixel, such a

  thinking can be stored in a single memory device, in this case it is the PROM memory 132, which corresponds to the column control conductors 72, which allows the PROM memory 103 to deliver, in accordance with the control conductors 74 lines, a single waveform to all 256 lines As such, the PROM 130 includes, by way of illustration, nine stored words, which are digital representations of nine predetermined voltage levels. example, each of these memory words has a duration of eight bits, which makes it possible to obtain sufficient precision for the applications of the present invention. These eight

  data bits delivered by the PROM memory 130 are app-

  plicated to a digital to analog converter 100 which

  delivers pre-voltage levels to its output terminal

determined corresponding.

  The output signal delivered by the counter 110

  is sent as a clock input signal to the comp-

  column divider / divider 112, which divides, according to a divi-

  binary, the clock input signal by the number of column conductors, 256 in this example In addition, the counter / divider 112 acts as a counter by delivering an output signal having a single clocked control edge after each 256-th appearance of its

input clock signal.

  The eight binary division output signals from the column counter / divider 112 are

  transmitted as addressing input signals to the mete

  PROM 132 and two-door RAM 120 recording mode addressing inputs The counter / divider 112 counting output signal is transmitted as a clocked command input signal

  to the line divider 114 and, through the provision

  level shift offset 96, at the counter / decoder 92 The line divider 114 divides, according to a binary division, its clock input signal by the number of line conductors, 256 in this example The eight output signals of binary divisors of lines 114 are transmitted in

  as addressing bits to PROM memory 132.

  Finally, the eight transmission lines of a si-

  gnal typical 8-BIT VIDEO DATA is also trans-

  set as addressing input signals to PROM 132 memory For the configuration, shown by way of illustration, of the PROM 132 memory shown in FIG. 2 and described in the appended text, the eight binary output signals coming from of line divider 114 are applied by forming the eight weight addressing bits the

  higher in PROM 132, the eight output signals

  tie of binary division delivered by the counter of

  lonnes / divisor 112 are the median address bits, and the eight VIDEO DATA signals are applied as

  the eight least significant addressing bits.

  In accordance with the principles of this invention

  tion, the ROM 132 contains words of video data

  at 9 bits, which provide individual DON- correction

  8-BIT VIDEO DATES, for each of the 65,536 pixels in the described embodiment Referring again to Figure 4, the nine lines of data output from PROM 132 are connected to RAM 120 in two ports RAM memory 120 stores the 9-bit video data word, to which access is made from PROM memory 132, thanks to the simultaneous addressing carried out from the column counter / divider 112 Simultaneously, the counter / divider 124 performs an operating cycle

  passing through its 256 addressing stages, recording se-

  basically the 256 words of 9-bit video data, which

  correspond to 256 columns, in a multiplexer 9-

  of-1,122 The divider 126 sequentially sends the selection input signals to the multiplexer 122, which

  allows to transmit a single bit position from each of 256 columns, then the immersed bit position

  next diat from each of the 256 columns, etc., at the serial data entry of the shift register 80.

  Referring now to Figure 10, there is shown a logical organization indicated as

  PROM 132 memory of the form of illustration

  Reading of FIG. 9 As described with reference to FIG. 9, the PROM memory 132 is arranged in the form of a 16 M device 9 (16,777,216 words of each 9 bits) containing 9 bit words used for transmit individual brightness data to each of the pixels

  of the display device 70 More particularly, the mete

  moire PROM 132, as shown in FIG. 10, contains, for each of the 65,536 pixels (256 lines x 256 columns) 256 9-bit digital words, which represent

  the corrected numerical values of the corresponding 256 levels

  8 bits of video input data.

  In the representation of FIG. 10, for the pixel located at the intersection of row 1 and column 1, a word of video input data O (in binary: 00000000) corresponds to a word of video data corrected to 9 bits equal to 1 (in binary: 000000001); an 8-bit video input data word equal to 1 (in binary: 00000001)

  corresponds to a corrected 9-bit video data word

  corresponding to 3 (in binary: 000000011); an 8-bit video input data word corresponding to 2 (in binary:) corresponds to a 9-bit corrected video data word equal to 4 (in binary: 000000100); an 8-bit video input data word equal to 3 (in binary: 00000011) corresponds to a 9-bit corrected video data word equal to 6 (in binary: 000000110) ;, a video input data word 8-bit equal to 254 (in binary: 11111110) corresponds to a corrected 9-bit video data word equal to 332 (in binary: 101001100); and an 8-bit video input data word equal to 255 (in binary: 11111111) corresponds to a corrected 9-bit video data word equal to 334 (in binary: 101001110) Although this is not represented in a way explicit, it is expected that the corrections for the 256 words of 8-bit video data may be different for each of the 65,536 pixels of the

  display panel 70 taken by way of illustration.

  Those skilled in the art will note that if there is to be an increase in the sensitivity of the corrected digital value of each video input word, the length of each of the 16 M words in the PROM 132 memory must be increased from the new one. shown for illustration in this example, and the number of intervals of

  each word of video data must be increased accordingly

  corresponding Such an increase allows more degrees

  precise brightness correction.

  After describing a device and a method for correcting undesirable variations in brightness

  individual pixels of a pan display

  flat and matrix addressing, subject to modification

  control voltage, the corrections made to the control voltage being produced by

  digital / analog circuits in response to meteorological data

  moralized in a PROM memory, it remains to describe

  which way such correction data is obtained

  naked. With reference to FIG. 11, there is shown by way of illustration a test assembly which can be

  used to determine the brightness of individual pixels

  duels of a flat panel display device 150 The test set-up uses a calculation processor 152 which

  can typically be a standard personal computer

  dart, wherein the processor 152 includes a commercial graphics adapter 154, which can typically

  be an extended standard graphics adapter (EGA)

  set to deliver digital video output data

  meric instead of analog data.

  The digital video data delivered by the processor 152 is transmitted to a video data processor 156, which includes a video RAM memory (VRAM) 158, a multiplexer 160, a PROM memory 162, a converter.

  digital / analog 164 and a module 166 used to pro-

  duce timing and control signals in the test setup The output signal delivered by the PROM memory 162 is transmitted via a digital / analog converter 164 to the line driver stage 172 , in a way that generally resembles the

  structure of the embodiments of Figures 4 to 9.

  In a similar manner, the video data coming from the VRAM memory 158 are transmitted via a multiplexer 160 to a column driving stage 170 The control currents delivered by the driving stage of

  lines 172 and through the column attack stage 170

  an electron emission at the pixels of the device

  150 positive display located at intersections

rows and columns.

  The memory elements and logic elements of the video data processor 156 store one or more lines of video data and transfer it in a sequence

  suitable in display drive stages 170, 172.

  The display device 150 is regenerated one line at a time. The calculation processor 152 performs a

programmable image control.

  To develop light correction data

  thinness in PROM memory, an analog converter

  current / digital current measurement 168 is interposed between the calculation processor 152 and the drive stages, 172, since it is known that the brightness of the display device is a direct result of the current

  snapshot of the beam at each pixel The

  Rant penetrating into the driving stages 170 and 172, which deliver the beam current, is detected and amplified to appropriate analog / digital levels. A positionable line register, which is present in the calculation processor 152, is provided. for the selection of

  conductor which is measured When the circuits compara-

  teurs indicate that the desired conductor is being addressed, the detected current, which is followed, is retained

  and converted to a numeric value using a device

  tif of current measurement 168 and is read by a calculation processor 152 By programming a single pixel or a series of pixels of a line in an "applied" current state, the measurement of a single pixel or d 'a group of

  pixels, depending on the desired average formation.

  By executing a sequential command through each pixel, each group of pixels and conductors, we

  can measure the current profile which corresponds to the light

nosity.

  Using the measured data, one can calculate

  the correction factors stored in the PROM memory for applications which are either unique for each individual panel, or allow standard correction for all panels manufactured by means of a specific process In a first unique application of the panels, if the correction desired is done by row and by column, we can consider that this correction is

  the sum of two curved planes, one curved plan compared

  port to a first axis and the other curved relative to a second axis perpendicular to the first Such a system is shown in the embodiment of Figure 4, correction factors taken by way of illustration being shown in Figure 5 Once the data is collected for a panel, we can use different statistical means to develop a set of two

  curved planes, which minimizes error The process-

  calculation unit 152 of the test assembly of FIG. 11

  nit means incorporated there ideal for performing this

  function in a fast and uniform manner.

  In a second single application to the panel, if the desired correction system is addressed on the basis of an individual pixel, as described in the embodiment of Figure 9, then the measured values are taken for each pixel subtracted from 'a reference level and are converted into a desired format In this case, each pixel (addressed by a line and a column is associated with a corrected video display control voltage intended to be applied in place of each

desired video level.

  If it is desirable and if it seems appropriate to provide a single standard correction configuration,

  then we can measure a number of panels and

  biner their correction values so as to obtain the best set of correction configurations for a group of panels Again, the power of the integrated calculation processor 152 of the test assembly of FIG. 11 allows an evaluation and / or an application of different statistical solutions The standard correction of the panel can be applied either on a row and column basis,

either pixel by pixel.

  The generalized test set-up in Figure 11, which is used to measure the correction values for the brightness levels at the individual pixels of a display panel, can also be used to

  validate the resulting correction configurations.

  Although the principles of pre-

  invention in particular in relation to the structure

  presented in the figures, it will be noted that different modi

  Fications can be made for the practical implementation of the invention The scope of the invention is not

  supposed to be limited to the particular structure described here and on the contrary is defined by the scope of the claims

  which are indicated below.

Claims (19)

  1 Flat panel display device   (10; 70; 150) comprising a support structure (12) having   on a surface comprising a first set of conduc-   tors (16; 74 (1) 74 (256)) substantially parallel arranged   across said surface, and a second set of con-   ductors (14; 72 (l) 72 (256)) substantially parallel dis-   laid across said surface, said conductors (16; 74 (1) 74 (256>) of said first assembly intersecting said conductors (14; 72 (1) 72 (256)) of said second assembly, while being electrically insulated therefrom, and further comprising means (76 (1,1) 76 (256,256)) provided at each intersection (32) of said first and second sets of conductors for emitting an electron beam current in response to a potential difference between said intersecting conductors and a device (30) for controlling the current of the electron beam delivered by said emitting means at the level of each of said intersections ,.   characterized in that this device (30) comprises means constituting a first (92) source coupled   audit first set of conductors to send individual   dual to these conductors a first signal comprising a set of steps having different voltage levels; means constituting a second source (88),   coupled to said second set of conductors for their   see a brightness control signal, which is controlled   between a first reference potential and a second potential   reference tiel in response to a video input signal   binary coded, the voltage difference between the   lons voltage levels of said first signal applied individually to said first set of conductors (16; 74 (1) 74 (256)) and said second reference potential   of said brightness control signal applied to said se-   cond set of conductors (14; 72 (l) 72 (256)) produced   sant an electron beam current emanating from the emitting means located at the intersection (32) of the conductor of said first set of conductors coupled to said means constituting the first source and of the conductor of said second set of conductors, coupled to said means constituting the second source, said current of   electron beam varying as a function of said difference   voltage rence; and means (110-116, 100,96,156; 118-126,88,168) coupled to one of said means constituting the first and   second sources (92; 84-86) to adjust the amplitude of the   general delivered by these source means, the adjustment being effected on a predetermined quantity specific to   each conductor forming part of said set of conduc-   torers coupled to that of said source means consi- déré.   2 Device according to claim 1, character-   laughed in that said first set of conductors (16; 74 (1) 74 (256)) comprises line conductors and   that said second set of conductors (14; 72 (1) -   72 (256)) includes column conductors, said line conductors being perpendicular to said column conductors.   3 Device according to claim 1, character-   laughed in that said adjusting means (110-116, 100, 96, 156) are coupled to said means constituting the first source (92; 172), said adjusting means allowing a   adjustment of the voltage levels of each step of said en-   seems to be in steps for each driver of said first   seems to be drivers (16; 74 (1) 74 (256)).   4 Device according to claim 1, character-   laughed in that said adjusting means (118-126, 88, 170) are coupled to said means constituting the second source   (84-86,170), said adjustment means allowing a reduction   setting of said binary coded video input signal for each conductor of said second set of conductors (14; 72 (l) 72 (256)).   Device according to claim 1, characterized in that said adjusting means (110-116, 100, 96,   156; 118-126, 88, 170) are coupled to said means consisting   killing the first source and said means constituting the   second source, said adjustment means allowing the re-   setting the voltage levels of each step of said en-   seems to be in steps for each driver of said first   seems to be conductive, and also allowing the adjustment of said binary coded video input signal for each   conductor of said second set of conductors.   6 Device according to claim 1, character-   laughed in that said adjustment means are coupled to   said means constituting the second source, said means   adjustment allowing adjustment of said vi input signal   binary coded deo, for each of the intersections of said   first and second sets of conductors (14; 72 (l) - 72 (256), 16; 74 (1) 74 (256)).   7 Device according to claim 1, character-   laughed at that the tensions at each level of the   said set of steps of said first signal are selected   to provide successive levels of   current of the electron beam, which are associated conform- even binary progression.   8 Device according to claim 1, character-   laughed in that said means constituting the first source (92) comprise:   means (116) for storing representations   digital tions of each level of said set of voltage level steps; and means (100,96) responsive to said memory means for converting said digital representations   into analog voltage levels.   9 Device according to claim 8, character-   laughed in that said memory means comprise a   programmable read only memory (PROM) (116).   Comprehensive flat panel display nant:   a support structure (12) having a pre-   first surface comprising a first set of substantially parallel conductors (16; 74 (1) 74 (256)) arranged in   across said surface and a second set of conduc-   substantially parallel twists (14; 72 (1) 72 (256)) disposed across said surface, said conductors of said   first set of conductors intersecting said conduc-   teurs of said second set of conductors, while being electrically insulated therefrom; means (30) provided at each intersection (32) of said first and second sets of conductors for emitting an electron beam current in response to a potential difference between said crossing conductors; a front structure having a second surface adjacent to said first surface and comprising means located on said second surface and sensitive to a   electron beam current to produce a lumines-   cence; and means for controlling the current of the electron beam produced by said emitting means at each of said intersections,   characterized in that said control means comprises   nent: means constituting a first source (92)   coupled to said first set of conductors (16; 74 (1) -   74 (256)) to send them individually   first signal, which includes a set of steps of ni- different calves;   means constituting a second source (84-   82), coupled to said second set of conductors (14; 72 (l)   72 (256)) to send a signal to them   brightness command, which is controlled between a first po-   reference differential and a second reference potential in response to a binary coded video input signal, the voltage difference between the voltage level steps   of said first signal applied individually to said pre-   mier set of conductors and said second reference potential of said brightness control signal applied to said second set of conductors being sufficient to produce an electron beam current from the emitter means located at the intersection of the conductor of said first set of coupled conductors   to said means constituting the first source and the conduc-   tor of said second set of conductors coupled to said means constituting the second source, said current of   electron beam varying as a function of said difference   voltage rence; and means (110-116,100,96,156; 118-126,88,168) coupled to one of said means constituting the first and second sources for adjusting the amplitude of the signal delivered by these source means, the adjustment being carried out on a predetermined quantity specific to each conductor forming part of the set of conductors coupled to said source means.   11 flat panel display device according to claim 10, characterized in that said first set of conductors (16; 74 (1) 74 (256)) comprises line conductors and that said second set of conductors (14; 72 (î) 72 (256)) includes conductors   columns, said line conductors being perpendicular   to said column conductors.   12 flat panel display device according to claim 10, characterized in that said adjustment means (110-116,100,96,156) are coupled to said means constituting the first source (92; 172), said adjustment means allowing adjustment of the voltage levels   each conductor of said set of conductors (16; 74 (1) - 74 (256)).   13 flat panel display device according to claim 10, characterized in that said adjustment means (118-126,88,170) are coupled to said means constituting the second source (84-86), said adjustment means allowing adjustment of said video input signal   binary coded, for each conductor of said second en-   seems to be drivers (14; 72 (1) 72 (256)).   14 flat panel display device according to claim 10, characterized in that said means   adjustment devices are coupled to said means constituting the first   source (92) and said means constituting the second   source (84-86), said adjustment means allowing the   setting the voltage levels of each step of said en-   seems to be in steps for each driver of said first   seems to be conductive, and also allowing the adjustment of said binary coded video input signal for each   conductor of said second set of conductors.   Flat panel display device according to claim 10, characterized in that said means   adjustment are coupled to said means constituting the se-   source source (84-86), said adjustment means allowing adjustment of said binary coded video input signal, for each of the intersections of said first and second conductor assemblies.   16 flat panel display device according to claim 10, characterized in that the voltages at each level of said set of steps of said first signal are selected so as to provide successive levels of the electron beam current, which   are associated according to a binary progression.   17 flat panel display device according to claim 10, characterized in that said means constituting the first source (92; 172) comprise:   means (116) for storing representations   digital tions of each level of said set of voltage level steps; and means (100,96) responsive to said memory means for converting said digital representations to analog voltage levels. 18 flat panel display device according to claim 17, characterized in that said memory means comprise a programmable read only memory (PROM) (116).