FR2938082B1 - Procede de controle du retard de boucle dans un modulateur sigma-delta et modulateur mettant en oeuvre le procede - Google Patents
Procede de controle du retard de boucle dans un modulateur sigma-delta et modulateur mettant en oeuvre le procedeInfo
- Publication number
- FR2938082B1 FR2938082B1 FR0806078A FR0806078A FR2938082B1 FR 2938082 B1 FR2938082 B1 FR 2938082B1 FR 0806078 A FR0806078 A FR 0806078A FR 0806078 A FR0806078 A FR 0806078A FR 2938082 B1 FR2938082 B1 FR 2938082B1
- Authority
- FR
- France
- Prior art keywords
- modulator
- sigma
- loop delay
- controlling loop
- delta
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
- H03M3/37—Compensation or reduction of delay or phase error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/402—Arrangements specific to bandpass modulators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
- H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
- H03M3/456—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a first order loop filter in the feedforward path
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0806078A FR2938082B1 (fr) | 2008-10-31 | 2008-10-31 | Procede de controle du retard de boucle dans un modulateur sigma-delta et modulateur mettant en oeuvre le procede |
US13/127,040 US20120056765A1 (en) | 2008-10-31 | 2009-10-29 | Method for controlling the loop delay in a sigma-delta modulator, and sigma-delta modulator implementing said method |
PCT/EP2009/064321 WO2010049504A1 (fr) | 2008-10-31 | 2009-10-29 | Procede de controle du retard de boucle dans un modulateur sigma-delta et modulateur mettant en œuvre le procede |
EP09756277A EP2342829A1 (fr) | 2008-10-31 | 2009-10-29 | Procede de controle du retard de boucle dans un modulateur sigma-delta et modulateur mettant en uvre le procede |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0806078A FR2938082B1 (fr) | 2008-10-31 | 2008-10-31 | Procede de controle du retard de boucle dans un modulateur sigma-delta et modulateur mettant en oeuvre le procede |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2938082A1 FR2938082A1 (fr) | 2010-05-07 |
FR2938082B1 true FR2938082B1 (fr) | 2013-03-29 |
Family
ID=40765702
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0806078A Expired - Fee Related FR2938082B1 (fr) | 2008-10-31 | 2008-10-31 | Procede de controle du retard de boucle dans un modulateur sigma-delta et modulateur mettant en oeuvre le procede |
Country Status (4)
Country | Link |
---|---|
US (1) | US20120056765A1 (fr) |
EP (1) | EP2342829A1 (fr) |
FR (1) | FR2938082B1 (fr) |
WO (1) | WO2010049504A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2469473A (en) * | 2009-04-14 | 2010-10-20 | Cambridge Silicon Radio Ltd | Digital phase locked loop |
US8970414B2 (en) * | 2013-06-24 | 2015-03-03 | Broadcom Corporation | Tri-level digital-to-analog converter |
US9148168B2 (en) * | 2013-10-29 | 2015-09-29 | Analog Devices Global | System and method of improving stability of continuous-time delta-sigma modulators |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0399738A3 (fr) * | 1989-05-26 | 1991-05-08 | Gec-Marconi Limited | Convertisseur analogique-numérique |
US6473013B1 (en) * | 2001-06-20 | 2002-10-29 | Scott R. Velazquez | Parallel processing analog and digital converter |
US6879274B2 (en) * | 2003-02-24 | 2005-04-12 | Analog Devices, Inc. | Signal-conditioning and analog-to-digital conversion circuit architecture |
US7315269B2 (en) * | 2005-08-09 | 2008-01-01 | Analog Devices, Inc. | Continuous time ΔΣ modulator system with automatic timing adjustment |
JP2009518882A (ja) * | 2005-12-06 | 2009-05-07 | エヌエックスピー ビー ヴィ | シグマ・デルタ型のアナログ‐デジタル変換器 |
JP2009005275A (ja) * | 2007-06-25 | 2009-01-08 | Toshiba Corp | Pll回路、pll制御装置、及びpll制御方法 |
US8171335B2 (en) * | 2008-09-16 | 2012-05-01 | Mediatek Inc. | Clock timing calibration circuit and clock timing calibration method for calibrating phase difference between different clock signals and related analog-to-digital conversion system using the same |
-
2008
- 2008-10-31 FR FR0806078A patent/FR2938082B1/fr not_active Expired - Fee Related
-
2009
- 2009-10-29 WO PCT/EP2009/064321 patent/WO2010049504A1/fr active Application Filing
- 2009-10-29 EP EP09756277A patent/EP2342829A1/fr not_active Withdrawn
- 2009-10-29 US US13/127,040 patent/US20120056765A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
FR2938082A1 (fr) | 2010-05-07 |
WO2010049504A1 (fr) | 2010-05-06 |
US20120056765A1 (en) | 2012-03-08 |
EP2342829A1 (fr) | 2011-07-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20150630 |