FR2935578A1 - SYSTEM FOR TRANSMITTING A SYNCHRONIZATION SIGNAL - Google Patents

Abstract

The present invention relates to a transmission device comprising means (EXS) for extracting signals (CLK) and pulses (IMP1) of synchronous FV frequency signals (CLK) of a synchronization signal (SGO). According to the invention, it comprises: - means (DIVP) for producing a signal (SA) of frequency FA such that FA = FV / P; means (LFVO1) for producing from a signal (SCOMP1) a signal (SB) of frequency FB greater than FA; means (DIVQ) for producing a signal (SC) of frequency FC such that FC = FB / Q; means (DIVR) for producing a signal (CLR) of frequency FCLR such that FCLR = FC / R where P, Q and R are integers; means (COMP1) for comparing the signal (SA) with the signal (SB) delivering the signal (SCOMP1); - a counter (CPT_PCR1) which produces counting ramps (CSE_PCR); means (LATCH1) for making samples (PCRe) of the ramps (CSE_PCR).

Description

FIELD OF THE INVENTION The present invention relates to the field of video equipment.

The present invention relates more particularly to a system for transmitting a synchronization signal between two devices connected by a communication network. The invention is particularly useful when the equipment is video equipment, for example a video source and a display device, both using a common video frequency, for example 27 MHz, the synchronization signal being produced from a signal of frequency at 1 GHz. The communication network is packet-switched, for example of the IP (acronym for the English Internet Protocol) type, whether the network is wired (for example Ethernet (IEEE802.3)) or non-wired, (for example IEEE 802.16 D-2004). STATE OF THE ART Advances in the ability of IP networks to carry any type of signal (data or video) make it possible to use such networks as a backbone architecture for video studios. A major interest of this evolution is to have then a unique infrastructure for the transport of data. While in the past, several media were needed to carry different types of signals between equipment. The multiplexing properties offered by the IP layer make it possible to reduce to one the number of necessary media: an IP network that connects the different devices. In the state of the art, the synchronization of video equipment (cameras, etc ...) in a studio is achieved by the transmission of a synchronization signal commonly called Genlock or black burst. For example, the Genlock signal is composed of two synchronization signals, one is repeated every 40 ms and indicates the start of the video frame, the other is repeated every 64 s (for a standard format and less for a HD format) and indicates the beginning of the lines in the video frame. The waveforms of the synchronization signals are a function of the format of the image transmitted on the network. For example, for a high-definition image, the synchronization signal has a shape called tri-level (-300mV, OV, +300 mV). When a synchronization signal is routed to various equipment to be synchronized by a dedicated coaxial cable, it is ensured a constant transmission time without jitter (phenomenon called jitter in English). From such a signal, any equipment is able to reconstruct a timing clock specific to its operation that ensures that its operation is strictly in phase with all equipment connected to the same network. For example, two cameras synchronized by a Genlock signal traveling on a dedicated coaxial cable, each generate a video of a different content but rigorously in frequency and phase relative to each other. A known disadvantage presented by an IP / Ethernet network comes from the fact that it introduces a strong jitter in a signal transmission and in particular for the transmission of a synchronization signal. When such a signal is routed over an IP / Ethernet link to various equipment to be synchronized, this jitter results in temporal fluctuations in the duration with which the information carried by the synchronization signal reaches the equipment.

In the prior art, for a set of equipment, for example cameras, connected to an IP network, devices are known for reconstructing at each camera, a clock clock specific to this camera and allowing it to free from jitter. The principle of these devices is based on a strong attenuation of the amplitude of the jitter of the synchronization signal at the reception. It can thus be guaranteed that an image generated by a camera is strictly in phase with all the images generated by the neighboring cameras connected to the same network. Examples of such jitter video synchronization systems are described in PCT international application FR2007 / 050918, they act on digital signals called counter (or PCR which is the acronym for the English expression Program Clock Reference) , which are representative of reference clock signals. These very precise digital signals are supplied to cameras through a network so that they can locally reconstruct clock signals in phase with the reference clock. The creation of the digital signal conveyed on the network and the reconstruction of the clock signals are carried out by a sampling clock CLKech common to the transmission device and to the reception devices. In particular, this CLKech clock must be perfectly identical for the transmission device and all the reception devices. A disadvantage of the systems of the prior art is that the digital signal conveyed from the transmission device to the reception device is created from a counting ramp comprising time steps whose duration corresponds to the frequency of the signal. clock of the synchronization signal. Now it can be shown that this counting ramp can also be used to carry out a time marking service (or time labeling in English) and transmit time markers from the transmission side to the reception side: an example of such a transmission application is described in the French application FR 0852687. In this case, the minimum accuracy that can be achieved on the time marker also corresponds to the duration of a step of the counting ramp. For a video application where the clock frequency transmitted in the synchronization signal is equal to 27MHz, the duration of the walk corresponds to 37 nanoseconds. It is therefore not possible to transmit a time stamp with a temporal accuracy better than 37 ns: this can be a troublesome limitation.

In addition, some users prefer to work with standard time references equal to a second, a microsecond, or a nanosecond ... In this case, if we always place in the context of a video application we are interested in finding means for working with a decoupled frequency of the video frequency (27 MHz), for example a frequency equal to 1 GHz, to create the counting ramp while ensuring a transmission of the correct and synchronous synchronization of a clock 27 MHz. One of the aims of the present invention is to overcome this drawback in order to make it possible to create counting ramps whose steps have a duration which is different from the period of the clock frequency of the synchronization signal to be transmitted. DISCLOSURE OF THE INVENTION The technical problem that the present invention proposes to solve is to ensure a decoupling between the duration of the steps of the counting ramps used to create a signal to be conveyed between a transmission device and a reception device and to ensure that, on receiving a signal for this purpose, the present invention relates, according to a first aspect, to a transmission device able to transmit packets in a packet communication network, said device comprising means ( EXS) for extracting synchronous clock signals (CLK) and synchronous FV pulses (IMP1) of the signals (CLK) from a synchronization signal (SGO). According to the invention the device further comprises: - means (DIVP) for producing, from the pulses (IMP1) and said clock signals (CLK), a signal (SA) of frequency FA such that FA = FV / Where P is an integer; means (LFVOI) for producing from the signal (SCOMPI) a signal (SB) of frequency FB greater than FA; means (DIVQ) for producing, from the signal (SB), a signal (SC) of frequency FC such that FC = FB / Q where Q is an integer; means (DIVR) for producing from the signal (SC) a signal (CLR) of frequency FCLR such that FCLR = FC / R where R is an integer; means (COMP1) for comparing the signal (SA) with the signal (SB), said means (COMP1) delivering a comparison signal (SCOMPI); - a counter (CPT_PCRI) clocked by the signal (SB) and initialized by the signal (CLR), said counter (CPT_PCRI) produces counting ramps (CSE_PCR); means (LATCH1) for making samples (PCRe) of the ramps (CSE_PCR) by a signal (CLKech) derived from a synchronized time base on all the devices connected to said network; and - means (INTE) for transmitting a packet containing the sample (PCRe) in the communication network.

According to a second aspect, the present invention relates to a reception device able to receive packets in a packet communication network, said device comprising means (REC) for receiving packets from said network, said packets comprising samples (PCRr) said samples (PCRr) from data sampled by a signal (CLKech) from a synchronized time base on all the devices connected to said network, the means (REC) extracting said samples (PCRr) from the received packets. According to the invention, the device further comprises: - means (LFVCO2) for producing from a comparison signal (SCOMP2) a signal (SRA) of frequency FRA; a counter (CPT_PCR2) clocked by the signal (SRA), said counter (CPT_PCR2) produces counting ramps (CSR_PCR2); means (LATCH2) for making local samples (PCR_Loc) of the ramps (CSR_PCR2) by the signal (CLKech); and means (COMP2) for comparing said samples (PCRr) with said local samples (PCR_Loc), said comparison means (COMP2) delivering the comparison signal (SCOMP2); means (DIVJ) for producing from the signal (SRA) and counting ramps (CSR_PCR2), a signal (SRB) of frequency FRB such that FRB = FRA / J where J is an integer; means (LFVCO3) for producing from the signal (SCOMP3) a signal (SRC) of frequency FRC; means (DIVK) for producing from the signal (SRC) a signal (SRD) of frequency FRD such that FRD = FRC / K where K is an integer; means (COMP3) for comparing the signal (SRD) with the signal (SRB), said comparing means (COMP3) delivering a comparison signal (SCOMP3) - means (EMS) for generating frequency pulses (IMP2) (FV) from the signal (SRC) and the signal (SRD); means for reconstituting a synchronization signal from said pulses (IMP2) and the signal (SRD). According to a third aspect, the present invention relates to a synchronization system comprising a transmission device as defined above and at least one reception device as described above. Advantageously, the frequency FRA of the signal SRA of the reception device or devices is identical to the frequency FB of the transmission device. Advantageously, the frequency FRC of the device or of the receiving devices is identical to the frequency FV of the pulses IMP1 of the transmission device. According to one embodiment, the frequency FB of the transmission device of a synchronization system according to FIG. The invention is identical to the frequency FRA of the signal SRA of the receiving device (s) Brief description of the drawings The invention will be better understood by means of the description, given below for purely explanatory purposes, of an embodiment of The invention, with reference to the appended figures: FIG. 1 illustrates the transmission of Genlock information between two cameras connected by an IP / Ethernet network; - Figure 2 illustrates the interfacing between an analog domain and an IP / Ethernet network; FIG. 3 illustrates the regeneration of the Genlock signal on the reception side according to the prior art; FIG. 4 schematically represents an architecture of a phase-locked loop of a reception device according to the prior art; FIG. 5 illustrates the interfacing between an analog domain and an IP / Ethernet network according to the invention; FIG. 6 illustrates the regeneration of the Genlock signal on the reception side 15 according to the invention. DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION The present analog world is interfaced to the IP / Ethernet network on the sending side, and the IP / Ethernet network is interfaced to the analogue receiving world, as shown in FIG. same figure, the emission side consists of a Master Genlock (or Genlock master) MGE which is connected to an Analog / IP interface I_AIP. The Genlock MGE Master produces a Genlock SGO signal for I_AIP interfaces. The receiving side consists of two cameras (CAM1, CAM2) each connected to an IP / Analog interface 1_IPA. The 1_IPA interfaces that will eventually be included in the cameras themselves are responsible for reconstructing Genlock SG1, SG2 signals for cameras CAM1, CAM2. The cameras CAM1, CAM2 each produce a video signal SV1, SV2 which it is desired to synchronize perfectly.

The transmitting and receiving sides are interconnected by a packet-switched network which causes jitter appearing on the Genlock SGO signal.

A sampling clock CLKech, of Tech period, generated from a first synchronization layer, for example IEEEI 588, is addressed to the emission and reception sides. Indeed, the protocol PTP (acronym for Precision Time Protocol) based on IEEE1588 makes it possible to obtain a synchronization between the equipment connected on a network Ethemet of the order of the microsecond. In other words, the timebases of all devices evolve at the same time to an accuracy near the microsecond. These timebases can be used in this case to generate each their own CLKech sampling clock in the Tech period. The use of the IEEEI 588 layer is not a must. Any system that can provide a CLKech sampling time of Tech period on different devices connected on a network may be suitable. For example, it is possible to use a sampling clock of 5ms period resulting from a physical layer of wireless transmission.

In Figure 2, we detail the processing of Genlock SGO signal from MGE, within the I AIP interface. First, an EXS module extracts timing information from the SGO signal to retrieve a timing video clock (denoted Clk video in Figure 2). Specifically, the EXS module is responsible for generating a pulse (or a top) at each image start. In addition, the EXS module comprises an image counter, for example a 40 msec counter, which is not shown in FIG. 2. The output of this image counter evolves according to a counting ramp passing through each 0 at each start. image, that is to say every 40 ms if we consider the image counter cited above as an example. By ramp count is a signal stair steps. The steps have a unit height. This is called ramp excursion counting, the level difference between the highest steps and the lowest steps For example, the excursion of the counting ramp delivered by the image counter is equal to 40ms.Ft, where Fout is the frequency of the Clk video clock. The image counter successively delivers all the integer values from 0 to 40 ms.Fout-1. The video timing clock is used to clock a CPT_PCR counter. The output of the counter CPT_PCR is a counting ramp CSE_PCR, whose period is worth m image periods. All images, the counter CPT_PCR is reset, that is to say that the counting ramp CSE_PCR is reset to 0. The excursion of the counting ramp delivered by the image counter is equal to m.40ms. Foät is. The counter CPT_PCR successively delivers all the integer values from 0 to m.40 ms.Foät-1. Subsequently, an LCH module samples the counting ramp CSE_PCR at a rate given by the sampling clock CLKech, that is to say with a Tech period and thus produces PCRe samples that are sent over the network. and travel through a network interface (INTE block) to the receiving side. Figure 3 shows the receiving side according to the prior art. The I_IPA interface retrieves PCRe samples that have been sent over the network. These PCR samples are received through a network interface (INTR module) with a delay related to the transport between the transmitting device and the receiving device: the INTR module produces PCRr samples. The PCR samples, which have been produced at regular intervals on the transmit side, arrive at irregular intervals on the reception side: this is due mainly to the jitter introduced during transport on the network. PCRr samples are taken into account at regular Tech intervals, and as a result, most of the jitter introduced during packet transport is eliminated. The inaccuracy between the sampling times of transmission and reception is absorbed by a PLL1 phase-locked loop whose bandwidth is appropriate. The characteristics of the PLL1 loop guarantee CLK_outi reconstituted clock generation with reduced jitter. The phase locked loop PLL1 behaves as a system receiving PCRr samples and delivering: a reconstituted clock CLK_out1, a counting ramp CSR_PCR, and local samples PCR loc1. When the PLL1 loop operates in steady state, the PCRr samples are substantially equal to the PCR_loc samples. The reconstituted clock CLK_out1 clock a CPT image counter similar to the emission-side image counter, for example a 40 ms counter. The image counter CPT is reset at each passage of the count ramp CSR_PCR1 by 0. Between two successive initializations, the image counter CPT evolves freely and produces a top image which feeds a local Genlock generator, GEG to produce a reconstructed Genlock signal SG1, SG2 intended to synchronize the CAM1, CAM2 cameras. The reconstructed Genlock signal SG1, SG2, which is generated from the counting ramp CSR_PCR1 and reconstituted clock CLK_out1 is in phase with the Genlock SGO signal on the sending side, at the clock stroke. FIG. 4 represents an architecture of a PLL1 phase-locked loop used in an I_IPA interface according to the prior art. As shown in FIG. 4, the phase-locked loop PLL comprises: a sample comparator CMP1 which compares PCRr samples and local samples and delivers a sample comparison result, or an ERR error signal; a corrector CORI receiving the signal ERR and delivering a corrected error signal ERC; a parameterizable oscillator VCO1 receiving the corrected error signal ERC and delivering a reconstituted clock CLK out, the clock CLK_out, has a frequency Fout which depends on the signal ERC; a counter CPT_PCR1 which produces a counting ramp CSR_PCR1 according to a rate printed by the reconstituted clock CLK_out, and having an excursion m.40 ms.Fouc; a value maintenance system LATCH1, which generates local PCR_loci samples from the values of the counting ramp CSR_PCR1 at the times defined by the sampling clock CLKooh; FIG. 5 is a simplified illustration of the various components constituting an I_AIP transmission device according to the invention providing the interface between an analog domain and an IP / Ethernet network. The device I_AIP comprises means EXS for extracting clock signals CLK and pulses IMP1 of frequency FV, synchronous signals CLK from a synchronization signal SGO. To simplify the explanation, the frequency of the clock signal CLK is equal to 27 MHz and the frequency FV is equal to 25 Hz. The device I_AIP comprises: - means DIVP for producing, from pulses 20 and IMP1 signals clock CLK, a signal SA of frequency FA such that FA = FV / P where P is an integer; means LFVOI for producing from the signal SCOMPI a signal SB of frequency FB greater than FA, the means LFVOI have a function similar to the blocks COR1 and VCO1; Means DIVQ for generating, from the signal SB, a signal SC of frequency FC such that FC = FB / Q where Q is an integer; means COMP1 for comparing the signal SA with the signal SB, said means COMP1 delivering a comparison signal SCOMPI. One chooses to work with signals whose frequency has a value facilitating calculations. For example, we choose the frequency value FA equal to one second and we set the value of 1 GHz for FB.

This imposes P = 25 and Q = 109 so that a comparison between the signal SA and the signal SB is possible. In steady state, the signals SA and SB are both pulses at 1 Hz and are equal.

From these choices, the counting ramp period CPT_PCR1 is defined, preferably so that it is different from the pulse period IMP1. For this, we have: - a counter CPT PCRI clocked by the SB signal, at 1GHz in our example. The counter CPT_PCR1 is initialized by a CLR signal and produces counting ramps CSE_PCR, of unit steps; means DIVR for producing from the signal SC a CLR signal of frequency FCLR such that FCLR = FC / R where R is an integer. Following the previous example R defines in seconds the period of the counting ramp, for example R = 1001; - LATCHI means for making PCRe samples ramps CSE_PCR by a signal CLKech from a synchronized time base on all the devices connected to said network; and - INTE means for sending a packet comprising the PCRe sample in the communication network. FIG. 6 schematically illustrates the various components constituting a device for receiving an interface 1_IPA according to the invention. As in the prior art, the receiving device includes REC means for receiving packets from the network. The packets contain PCRI samples. from data sampled by a CLKech signal from a synchronized time base on all devices connected to said network. The REC means extract PCRr samples from the received packets. The device 1_IPA comprises a first stage operating at the frequency FB. This first stage consists of: - means LFVCO2 for producing from a comparison signal SCOMP2 a signal (SRA) of frequency FRA. For example, a frequency FRA equal to FB is equal to 1 GHz; a counter CPT_PCR2 clocked by the signal SRA of frequency FRA. Counter CPT_PCR2 produces counting ramps (CSR_PCR2), and excursion determined according to m of FRB and FV. For example the excursion EXC of the counter is chosen to be equal to m.FB / FV; - LATCH2 means for making local samples 1 o PCR_Loc CSR_PCR2 ramps by the CLKech signal; and COMP2 means for comparing the PCRr samples with the local PCR_Loc samples. The comparison means COMP2 deliver a comparison signal SCOMP2; The device I_IPA further comprises means DIVJ for producing, from the signal SRA and counting ramps CSR_PCR2, a signal SRB of frequency FRB such that FRB = FRA / J where J is an integer. In particular the means DIVJ are clocked by the signal SRA and initialized at each passage of the counting ramp CPT_PCR2 by a particular value PCR_REF between 0 and EXC-1. The DIJ means 20 deliver a synchronous pulse from the moment when the remainder of the division of CSR_PCR2 by J is equal to 0. For example J = 109. - means (LFVCO3) for producing from a comparison signal SCOMP3 a signal SRC of FRC period equal to FV. For example FRC = 25Hz; Means DIVK for producing, from the signal SRC, a signal SRD of frequency FRD such that FRD = FRC / K where K is an integer. For example K = 25, thus FRD is 1 Hz and the comparison between SRB and SRD can be made; means COMP3 for comparing the signal SRD with the signal SRB, said comparison means COMP3 deliver the comparison signal SCOMP3.

The device further comprises EMS means for generating pulses IMP2 of frequency FV from the signal SRC and the signal SRD. In particular, the means EMS are clocked by the signal SRTD and the signal SRC constitutes a signial of reset or reset to O. The device further comprises means GEG for reconstituting a synchronization signal from the pulses IMP2 and the signal SRD. The invention is described in the foregoing by way of example. It is understood that the skilled person is able to realize different variants of the invention without departing from the scope of the patent. 15

Claims (3)

REVENDICATIONS1. Transmitting device capable of transmitting packets in a packet communication network, said device comprising means (EXS) for extracting clock signals (CLK) and pulses (IMP1) of synchronous frequency FV of said signals (CLK) from a synchronization signal (SGO); characterized in that the device further comprises: - means (DIVP) for generating, from said pulses (IMP1) and said clock signals (CLK), a signal (SA) of frequency FA 10 such that FA = FV Where P is an integer; means (LFVO1) for producing from a comparison signal (SCOMPI) a signal (SB) of frequency FB greater than FA; means (DIVQ) for producing, from the signal (SB), a signal (SC) of frequency FC such that FC = FB / Q where Q is an integer; Means (DIVR) for generating from the signal (SC) a signal (CLR) of frequency FCLR such that FCLR = FC / R where R is an integer; means (COMP1) for comparing the signal (SA) with the signal (SB), said means (COMP1) delivering the comparison signal (SCOMPI); a counter (CPT_PCRI) clocked by the signal (SB) and initialized by the signal (CLR), said counter (CPT_PCR1) produces counting ramps (CSE_PCR); means (LATCH1) for making samples (PCRe) of the ramps (CSE_PCR) by a signal (CLKech) derived from a synchronized time base on all the devices connected to said network; and means (INTE) for transmitting a sample packet (PCRe) in the communication network. 2. Receiving device capable of receiving packets in a packet communication network, said device comprising means (REC) for receiving packets from said network, said packets comprising samples (PCRr), said samples (PCRr) coming from data sampled by a signal (CLKech) derived from a synchronized time base on all the devices connected to said network, said means (REC) extracting said samples (PCRr) from the packets received; characterized in that the device further comprises: - means (LFVCO2) for generating from a comparison signal (SCOMP2) a signal (SRA) of frequency FRA; a counter (CPT_PCR2) clocked by the signal (SRA), said counter (CPT_PCR2) produces counting ramps (CSR_PCR2); means (LATCH2) for making local samples (PCR_Loc) of the ramps (CSR_PCR2) by the signal (CLKech); and means (COMP2) for comparing said samples (PCRr) with said local samples (PCR_Loc), said comparison means (COMP2) delivering the comparison signal (SCOMP2); means (DIVJ) for producing from the signal (SRA) and the counting ramps (CSR_PCR2), a signal (SRB) of frequency FRB such that FRB = FRAIJ where J is an integer; means (LFVCO3) for producing from a comparison signal (SCOMP3) a signal (SRC) of frequency FRC; means (DIVK) for producing from the signal (SRC) a signal (SRD) of frequency FRD such that FRD = FRC / K where K is an integer; means (COMP3) for comparing the signal (SRD) with the signal (SRB), said comparing means (COMP3) delivering the comparison signal (SCOMP3) - means (EMS) for generating frequency pulses (IMP2) (FV) from the signal (SRC) and the signal (SRD); means for reconstituting a synchronization signal from said pulses (IMP2) and the signal (SRD). 3. Synchronization system comprising a transmitting device according to Claim 1 and at least one receiving device according to Claim 2. 5. Synchronization system according to the preceding claim, characterized in that the frequency (FRA) of the signal (SRA) of the receiving device or devices is identical to the frequency (FB) of the transmission device. 5. Synchronization system according to the preceding claim characterized in that the frequency (FRC) of the receiving device is identical to the frequency (FV) of the impulse (IMP1) of the transmitting device.