FR2920941A1 - FINE COMPENSATION OF A PACKAGE TRANSPORT DURATION FOR A SYNCHRONIZATION OF EQUIPMENT CONNECTED BY AN IP NETWORK - Google Patents

Abstract

The present invention relates to the field of video equipment. More particularly, it relates to a reception device capable of receiving packets in a communication network which comprises means for: receiving packets containing network samples originating from data sampled all Tech periods, where Tech is obtained from a database time synchronized on all stations in the network. i is an index which uniquely identifies a received sample PCRr, i, the received sample PCRr, i + 1 succeeds chronologically to the PCRr sample, i; - regenerate a counting ramp CSR_PCR1 using a locking loop phase PLL1 receiving the samples PCRr, iand delivering samples PCR_loc1, all Tech periods and a reconstituted clock; - initialize, at all zero crossings of the counting ramp CSR_PCR1, a CPT image counter which is clocked by the reconstituted clock CLK_out1 ; According to the invention, the device comprises means for: - determining a DeltaEientre difference value two samples received PCRr, executive icons; - storing DeltaEi difference values; - determining an average value << T 324> E> Ides DeltaEi values; - Add the mean value << T 324> E> I to the samples received PCRr, i.

Description

1 FINE COMPENSATION OF A PACKET TRANSPORT DURATION FOR A SYNCHRONIZATION OF EQUIPMENT CONNECTED BY AN IP NETWORK Field of the invention The present invention relates to the field of video equipment. The present invention relates more particularly to a device for receiving a synchronization signal on a packet-switched communication network, for example of the IP (acronym for Internet Protocol) type, whether the network is wired. (for example Ethernet (IEEE802.3)) or wireless, (for example IEEE 802.16 D- 2004).

STATE OF THE ART Advances in the capacity of IP networks to transport all types of signals (data or video) make it possible to use such networks as backbone architecture for video studios. A major advantage of this development is then having a unique infrastructure for data transport. While in the past, several media were needed to transport different types of signals between devices, the multiplexing properties offered by the IP layer make it possible to reduce the number of media required to one: an IP network that connects the different devices.

In the state of the art, the synchronization of video equipment (cameras, etc.) in a studio is carried out by the transmission of a synchronization signal commonly called Genlock or black burst. For example, the Genlock signal is composed of two synchronization signals, one is 2 repeated every 40 ms and indicates the start of the video frame, the other is repeated every 64 s (for a standard format and less for HD format) and indicates the start of lines in the video frame. The waveforms of the synchronization signals depend on the format of the image transmitted over the network. For example for a high definition image, the synchronization signal has a so-called tri-level form (-300mV, Ov, +300 mv).

When a synchronization signal is routed to various equipment to be synchronized by a dedicated coaxial cable, a constant transmission duration is ensured, without jitter (a phenomenon called jitter in English). From such a signal, any device is able to reconstruct a timing clock specific to its operation which guarantees that its operation is strictly in phase with all the devices connected to the same network. For example, two cameras synchronized by a Genlock signal circulating on a dedicated coaxial cable, each generate a video of different content but rigorously in frequency and in phase with respect to each other.

A known drawback presented by an IP / Ethernet network comes from the fact that it introduces a strong jitter in a signal transmission and in particular for the transmission of a synchronization signal. When such a signal is conveyed by an IP / Ethernet link to various devices to be synchronized, this jitter results in temporal fluctuations in the duration with which the information carried by the synchronization signal reaches the devices.

In the prior art, devices are known for reconstructing, at the level of each camera, a timing clock specific to this camera making it possible to overcome jitter. The principle of these devices is based on a strong attenuation of the amplitude of the jitter of the synchronization signal at the reception level. It is thus possible to guarantee that an image generated by a camera is strictly in phase with all the images generated by neighboring cameras connected to the same network. Examples of such jitter attenuation devices are described in the international PCT application FR2007 / 050918, they act on so-called counter digital signals (or PCR, which is the acronym of the English expression Program Clock Reference ), which are representative of very precise reference clock signals. These digital signals are supplied to cameras through a network so that they can locally reconstruct clock signals in phase with the reference clock.

The reception device according to the prior art comprises means for: receiving packets containing network samples originating from data sampled every period Teh; - regenerate a CSR_PCR1 count ramp using a PLL1 phase locked loop; -initialize a second counter CPT for all zero crossings of said first counter CSR_PCR1; - Generate image tops for all zero crossings of said second CPT counter; and - reconstituting a synchronization signal from said image tops.

The PLL1 phase locked loop (PLL is the acronym of the English expression Phase Locked Loop) of the receiving device behaves like a low pass filter which partially attenuates the jitter present on samples received PCRr which have circulated on the network. 4 However, this international patent application does not mention the problem of reducing or eliminating a residual delay in the synchronization of two devices caused a priori correction of the effects of network latency. In fact, in reception devices according to the prior art, it is considered that the duration of the information transport between the two items of equipment is fixed and corresponds to a Tech period of the sampling clock. This assumption is correct in the first order, however it does not take into account variations in the Tech period of the sampling clock at the level of the transmission as well as of the reception.

Thus, in the reception devices according to the prior art to compensate for the duration of transport of the information on the network, a fixed value OFFSET is added to each received sample PCRr at a flat rate which corresponds to the theoretical difference between two consecutive samples. The invention relates to fine compensation for the delay linked to the duration of transport of the information and requires a preliminary measurement of these effects. Disclosure of the invention To this end, the present invention relates to a reception device capable of receiving packets in a packet communication network comprising at least two stations, said device comprising means for: - receiving packets containing samples of said network, said samples coming from data sampled every period Teh, where Teh comes from a time base synchronized on all the stations of said network, i being an index univocally identifying a received sample PCRr., the received sample PCRr. ,. ,, chronologically following the received sample PCRr .; regenerate a PCR Modulus excursion CSR_PCR1 count ramp using a PLL1 phase locked loop receiving the PCR samples. and further delivering local samples PCR_loc1 all Tech periods and a reconstructed clock CLK_out 1; - initialize, at all zero crossings of the counting ramp CSR_PCR1, a CPT image counter which is clocked by the reconstituted clock CLK_out1; - generating image tops for all zero crossings of said CPT image counter; and reconstituting a synchronization signal from said image tops; characterized in that it comprises means for: determining a difference value DE, between two consecutive PCR received samples; - store DE deviation values. ; 20 - determine an average value <AE>, DE values. ; - Add the mean value <AE> i to the received PCR samples. Brief Description of the Drawings The invention will be better understood with the aid of the description, given below for purely explanatory purposes, of an embodiment of the invention, with reference to the appended figures: FIG. 1 illustrates the transmission of Genlock information between two cameras connected by an IP / Ethernet network; - Figure 2 illustrates the interfacing between an analog domain and an IP / Ethernet network; FIG. 3 illustrates the regeneration of the Genlock signal on the reception side according to the prior art; 6 - Figure 4 schematically shows an architecture of a phase locked loop of a reception device according to the prior art; FIG. 5 schematically represents an architecture of a phase locked loop of a reception device according to the invention. Detailed Description of Embodiments of the Invention The current analog world is interfaced to the IP / Ethernet network on the send side, and the IP / Ethernet network is interfaced to the analog world on the receive side, as illustrated in Figure 1. On this same figure, the transmission side consists of a 15 MGE Genlock master (or Genlock master) which is connected to an I_AIP Analog / IP interface. The Genlock MGE Master produces a Genlock SGO signal intended for the AIP I interfaces. The reception side consists of two cameras (CAM1, CAM2) each connected to an IP / Analog I_IPA interface 20. The I_IPA interfaces which will eventually be included in the cameras themselves are responsible for reconstructing the Genlock SG1, SG2 signals intended for the cameras CAM1, CAM2. The cameras CAM1, CAM2 each produce a video signal SV1, SV2 which one wishes to synchronize perfectly. The transmission and reception sides are linked together by a packet-switched network which is the source of a jitter appearing on the Genlock SGO signal. A sampling pulse, at period Teh, is generated from a first synchronization layer, for example IEEE1588, is addressed to the transmission and reception sides. Indeed, the PTP 35 protocol (acronym for Precision Time Protocol) based on IEEE1588 makes it possible to obtain synchronization between the devices 7 connected on an Ethernet network of the order of one microsecond. In other words, all the time bases of each device evolve at the same time to a precision close to the order of a microsecond.

These time bases can be used in this case to each generate their own sampling peak at the period Teh. The use of the IEEE1588 layer is not a necessary step. Any system making it possible to provide sampling tops during the Tech period on the various equipment connected on a network may be suitable. It is for example possible to use a sampling pulse with a period of 5 ms coming from a physical wireless transmission layer.

In FIG. 2, we detail the processing of the Genlock SGO signal originating from MGE, within the I_AIP interface. First of all, an EXS module extracts synchronization information from the SGO signal in order to recover a timing video clock (denoted Clk video in FIG. 2). More precisely, the EXS module is in charge of generating a top image at each start of an image. In addition, the EXS module includes an image counter, for example a 40 ms counter, which is not represented in FIG. 2. The output of this image counter changes according to a counting ramp passing through 0 at each image period, that is to say every 40 ms if we consider the image counter cited as an example above. The image counter delivers a staircase signal. The steps have a unit height. The excursion of the signal, that is to say the height corresponding to the difference in level between the lowest high of the steps and the highest of the steps is equal to 40ms.Fout, where Fout is the frequency of the Video Clk clock. The CPT counter successively delivers all the integer values from 0 to 40 ms Fout-1. 8 The timing video clock is used to clock a CPT_PCR counter. The output of the CPT_PCR counter is a CSE_PCR counting ramp, the period of which is equal to m image periods. Every m images, the CPT_PCR counter is reset, ie the CSE_PCR counting ramp is reset to 0. The counting ramp is used to designate a staircase signal. The steps have a unit height (or AC count increment). The excursion of the signal, that is to say the height corresponding to the difference in level between the lowest of the steps and the highest of the steps is equal to m.40ms.Foät. The counter CPTPCR1 successively delivers all the integer values from 0 to m.40 ms Fout-1.

Subsequently, an LCH module samples the CSE_PCR count ramp and all Tech periods to produce PCRe samples. These PCRe samples are sent over the network and circulate to the reception side through a network interface (INTE block). FIG. 3 represents the reception side according to the prior art. The I_IPA interface retrieves the PCRe samples that have been sent over the network. These PCRe samples are received through a network interface (INTR module) with a delay linked to the transport between the sending device and the receiving device: the INTR module produces PCRr samples. The PCRe samples, which were produced at regular Tech intervals on the transmit side, arrive at irregular intervals on the receive side: this is mainly due to the jitter introduced during transport on the network. PCRr samples are taken into account at regular Tech intervals and therefore most of the jitter introduced during packet transport is eliminated. The imprecision between the sampling instants of the transmission and the reception is absorbed by a phase locked loop PLL1 of which the bandwidth is appropriate. The characteristics of the PLL1 loop guarantee a reconstituted clock generation CLKout, with reduced jitter.

The PLL1 phase locked loop behaves like a system receiving PCRr samples and delivering: - a reconstituted clock CLK_out1, - a counting ramp CSR_PCR1 and, - local samples PCR_loc1. When the PLL1 loop operates in steady state, the PCRr samples are substantially equal to the PCR_loc1 samples. The reconstituted clock CLK_out, rates a CPT image counter similar to the image counter on the transmission side, for example a 40 ms counter. The CPT image counter is reset each time the CSR_PCR1 count ramp goes through 0. Between two successive initializations, the CPT image counter evolves freely and produces a top image which supplies a local Genlock generator, GEG to produce a reconstructed Genlock signal SG1, SG2 intended to synchronize the cameras CAM1, CAM2. The reconstructed Genlock signal SG1, SG2, which is generated from the counting ramp CSR_PCR1 and from the reconstructed clock CLK_out, is in phase with the Genlock signal SGO on the transmission side, up to the clock stroke.

FIG. 4 represents an architecture 30 of a phase locked loop PLL1 employed in an interface I IPA according to the prior art. As represented in FIG. 4, the phase locked loop PLL1 comprises: a comparator of samples CMP1 which compares the samples PCRr and local samples and delivering a result of comparison of the samples, or an error signal ERR; 10 - a corrector COR1 receiving the signal ERR and delivering a corrected error signal ERC; a configurable oscillator VCO1 receiving the corrected error signal ERC and delivering a reconstituted clock CLK_out1, the clock CLK_out, has a frequency Fout which depends on the signal ERC; a counter CPT_PCR1 which produces a counting ramp CSR_PCR1 according to a rate printed by the reconstituted clock CLK_out; a system for maintaining the LATCH value, which generates local samples PCR_lac, from the values of the counting ramp CSR_PCR1 at the instants Tech;

FIG. 5 illustrates a phase locked loop PLL1 of a receiving device PLL1 according to the invention. The PLL1 loop also comprises means for: determining a difference value DE, between two consecutive PCR received samples; 20 - store DE deviation values. ; - determine an average value <AE>, DE values. ; - Add the mean value <AE> i to the received PCR samples. For example, the PLL1 loop includes a device REC1 which receives the various PCR samples received. Advantageously, the means 30 for determining the difference value DE, between two consecutive received samples deliver a modulo PCR Modulus result. That is to say that for each index i, the device REC1 determines DEi from a difference between PCRr,. ,, and PCRc, i if (PCRr, i +, - PCRr.) Is positive and 25 11

determines DE, from the expression PCR_Modulus + (PCRr ,, +, - PCRr.) if (PCRr ,, +, - PCRr.) is negative. Subsequently, the device REC1 stores the deviation value DE, then delivers an average value of the deviation DE .. Advantageously, the means for determining an average value <AE> deliver a value equal to 0.1 AE._1 + 0.9 DE ,. For each index i, the mean value <AE>. 10 is added to received PCR samples.

The invention is described in the foregoing by way of example. It is understood that a person skilled in the art is in a position to produce various variants of the invention without, however, departing from the scope of the patent.

Claims (3)

1. Receiving device capable of receiving packets in a packet communication network comprising at least two stations, said device comprising means for: receiving packets containing samples from said network, said samples coming from data sampled every period Teh, where Teh comes from a time base synchronized on all the stations of said network, i being an index univocally identifying a received sample PCRr., the received sample PCRr,. ,, chronologically succeeding the received sample PCRr. ; - regenerate a CSR_PCR1 counting ramp of Modulus PCR excursion using a PLL1 phase locked loop receiving the PCR samples. and further delivering local samples PCR_loc1 all Tech periods and a reconstructed clock CLK_out 1; - initialize, at all zero crossings of the counting ramp CSR_PCR1, a CPT image counter which is clocked by the reconstituted clock CLK_out1; - generating image tops for all zero crossings of said CPT image counter; and - reconstituting a synchronization signal from said image tops; characterized in that it comprises means for: determining a deviation value DE. between two consecutive PCR received samples; store DE deviation values. ; determine an average value <AE>, DE values. ; -Add the mean value <AE> i to the samples received PCR. 35 2. Receiving device according to claim 1, characterized in that the means for determining the deviation value DE, between two consecutive received samples deliver a result 5 modulo PCRModulus. 3. Receiving device according to claim 1, characterized in that the means for determining an average value <AE> deliver a value equal to o, l AE._1 + 0.9 DE ,.